NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

2006 MAPLD International Conference

Ronald Reagan Building and International Trade Center
with a session at the Smithsonian National Air and Space Museum

Washington, D.C.

September 26-28, 2006

Session W: Verification of Large Designs and Related Design Methodologies

Wes Powell, NASA Goddard Space Flight CenterJohn Lach, University of Virginia
Session Chairs:
Wes Powell, NASA Goddard Space Flight Center
John Lach, University of Virginia

Session W will be held on Tuesday, September 26, 2006 from 4:10 - 5:40 pm and on Wednesday, September 27, 2006 from 4:05 - 5:35 pm.  Both sessions will be held in Hemisphere B.


This session will address the issues in verification strategies for large FPGA designs for space applications developed using high-level design tools.

Designers on upcoming missions are being faced with the dilemma of how to develop large, high performance FPGA applications while still being able to verify them with an acceptable degree of rigor. The size of today's FPGAs and the complexity of the applications are driving designers to use high-level tools where the design is specified at higher level of abstraction that conventional hardware description languages. However, with these tools the designer can be very removed from the actual logic that is being produced. A similar situation exists with the use of third party IP cores, which are used as "black boxes" in designs and where the degree and rigor of their testing may be unknown.

Hence, a very real challenge is how to verify designs developed with these tools to ensure that they are sufficiently robust for space applications. Spaceflight FPGA designs, especially those for mission and safety-critical applications, are often analyzed at the gate level. It will be very difficult (if not impossible) to perform this level of verification with the output of high-level tools and third party IP cores. Tools that automatically insert redundancy into synthesized netlists will complicate this even further.

Topics for discussion:

  1. Verification methods and strategies for large FPGA applications developed with high-level design tools and third party IP cores.
  2. Assessments of appropriate spaceflight uses for these applications.


Tuesday, September 26, 2006

Submission 139 (Session A)
“Implementing Space Shuttle Data Processing System Concepts in Programmable Logic Devices”
Roscoe C. Ferguson, Robert Tate, and Hiram C. Thompson
United Space Alliance
Abstract: 139_ferguson_a.html

Submission 141 (Poster Session)
"Let’s Get Practical: Reuse Is Recycling"
Tom Dewey and Michael Lee
Mentor Graphics Corporation
Abstract: 141_dewey_a.html

Submission 184 (Session E)
"In-System Test for FPGAs"
Dan Gardner1, Ron Press1, and Melanie Berg2
1Mentor Graphics
2NASA GSFC/Muniz Technologies
Abstract: 184_gardner_a.html

Submission 240 (Poster Session)
"Design Assurance"
Dave Rinehart1 and Ravi Pragasam2
1Aldec Corporation
2Actel Corporation
Abstract: 240_rinehart_a.html

Submission 1008 (Poster Session)
“In-Circuit Verification and Validation of FPGA Systems”
Gregory B. Davis
Abstract: 1008_davis_a.html

Submission 1009 (Poster Session)
“Topics to Consider When Analyzing a Flight FPGA Design”
Michael J. McDonnell
Ball Aerospace & Technologies Corporation
Abstract: 1009_mcdonnell_a.html


Wednesday, September 27, 2006

Submission 135 (Session B)
"FPGAs: Quality through Model Based Design and Implementation"
Yves LaCerte1 and
Yang Zhu2
1Rockwell Collins
General Dynamics
Abstract: 135_lacerte_a.html

Submission 145 (Session E)
"A Formalized Verification Methodology for Soft IP Cores in Safety-Critical Applications"
Travis Lenhart and John Lach
University of Virginia
Abstract: 145_lenhart_a.html

Submission 146 (Poster Session)
"Verification & Validation: What Can We Learn From Software Engineers?"
Scott Bingham, John Knight, John Lach, and Elisabeth Strunk
University of Virginia
Abstract: 146_bingham_a.html

Submission 167 (Poster Session)
"A Refinement-based Methodology for Implementation Design and Semi-automatic Verification on an FPGA"
A. Mcewan
University of Surrey
Abstract: 167_mcewan_a.html

Submission 215 (Poster Session)
"Unified System Verification Using a VHPI Abstraction Layer"
Petersen F. Curt1, Daniel K. Price2, Michael R. Bodnar2, and James P. Durbano1
EM Photonics, Inc.
2University of Delaware
Abstract: 215_curt_a.html

Submission 253 (Session E)
"Increasing Confidence of Complex Hardware in Safety-Critical Avionics Using Formal Methods"
Kristoffer Karlsson and Håkan Forsberg
Saab Avitronics
Abstract: 253_karlsson_a.html


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