“Implementing Space Shuttle Data Processing System Concepts in Programmable Logic Devices”
Roscoe C. Ferguson, Robert Tate, and Hiram C. Thompson
United Space Alliance
Since 1981, the Space Transportation System (STS) or Space Shuttle has been the workhorse of the United States Man Space Program. Its primary and backup flight control system (consisting of five computers, software, and a network of twenty-four buses) was considered to be state of the art at it’s time of inception. It was one of the first successful implementations of a redundant digital fly by wire avionics system and has exhibited a near perfect performance record over its service life. While the heart of the Space Shuttle avionics system is implemented in out-dated and hard to maintain technology, most of the design concepts are still relevant for modern avionics systems. This same problem will exist for new systems designed today that must provide a long service life. Programmable Logic Devices (PLD) offer promise in the ability to preserve existing assets and the flexibility required to evolve system concepts over time. To investigate the promise of PLDs, two key Space Shuttle avionics concepts were prototyped in Field Programmable Gate Arrays (FPGA).
Each of the five Space Shuttle data processing units is an IBM AP101S General Purpose Computer (GPC). Each computer consists of a Central Processing Unit (CPU) and an Input/Output Processor (IOP). The CPU performs all “data crunching” and receives its input from and performs output to the IOP which is connected to each of the twenty-four data buses. To support redundancy management, the GPCs are synchronized using a hardware discrete interface (each GPC sends a three bit discrete code to the others and receives the corresponding code from four external GPCs) and software sync loop algorithms in the Flight Computer Operating System (FCOS).
The first concept prototyped was the Space Shuttle primary flight computer. The CPU and IOP of the AP101S were implemented in an Altera Stratix FPGA. The flight software from the STS-114 mission was successfully executed on this FPGA. This provides an example of the capability to preserve existing assets. The second concept prototyped was the Space Shuttle computer synchronization concept. The FCOS software sync algorithms were implemented in hardware to produce a prototype hardware synchronization chip than can support a four computer redundant set. This chip replaces the hardware discrete interface with a serial bus interface and uses “messages” instead of parallel discrete signals. This change allows for the built in exchange and voting of state data. Each chip provides an interface for a host processor. The host processor can provide state data to the synchronization chip for voting per frame (50 Hz) and receives interrupts from the chip to indicate the start of a minor frame along with information including major/minor cycle number, the results of data state voting (including isolation) and sync failure indication. The prototype synchronization chip was interfaced to a NIOS II RISC processor executing applications running on top of a MicroC/OS-II RTOS on an Altera Stratix FPGA. A configuration of two NIOS II processors were synchronized for days using the synchronization chips without failure.
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