NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

2004 MAPLD Technical Program

Ronald Reagan Building and International Trade Center
Washington, D.C.

September 8-10, 2004

Session D. Logic Design and Processors

Thursday, September 9, 2004

Keith Bergevin of the Defense Microelectronics Activity (DMEA)Robert Hodson - NASA Langley Research Center
Session Chairs:
Keith Bergevin - Defense Microelectronics Activity (DMEA)
Robert Hodson - NASA Langley Research Center


11:35 am

Submission 110
"SEU Mitigation Techniques for Xilinx Virtex-II Pro FPGA"
Mandy M. Wang and Gary S. Bolotin, Jet Propulsion Laboratory
Abstract: wang_a.doc
Presentation: d110_wang_s.ppt

12:00 pm

Lunch In The Atrium Ballroom

1:15 pm Invited History Talk
"The Past, Present, and Future of Human Space Exploration"
John W. Young
Associate Director, Technical, NASA Johnson Space Center
Presentation: young_s.ppt
Video: young.wmv  (GSFC library server)
2:30 pm Submission 177
"Soft Errors in Adder Circuits"
Rajaraman Ramanarayanan, N. Vijaykrishnan, Yuan Xie and Mary Jane Irwin, and Kerry Bernstein
Pennsylvania State University
Abstract: ramanarayanan_a.pdf
Presentation: d177_ramanarayanan_s.ppt
2:55 pm

Submission 200
"Super-Sized Multiplies: How Do FPGAs Fare in Extended Digit Multipliers?"
Stephen Craven, Cameron Patterson, and Peter Athanas
Virginia Polytechnic Institute and State University
Abstract: craven_a.doc
Presentation: d200_craven_s.ppt
Paper: d200_craven_p.doc

3:20 pm BREAK In The Atrium Hall
4:00 pm

Finite State Machine Theme

Submission 219
"Fault Tolerant Design Techniques for Asynchronous Single Event Upsets within Synchronous Finite State Machine Architectures"
Melanie Berg, Ball Aerospace & Technologies Corp.
Abstract: berg_2_a.doc
Presentation: d219_berg_s.ppt
Paper: d219_berg_p.doc

Submission 160
"Fault Tolerant State Machines"
Gary Burke and Stephanie Taft, Jet Propulsion Laboratory
Abstract: taft_a.doc
Presentation: d160_burke_s.ppt
Paper: p160_burke_p.doc

Submission 118
"Automated FSM Error Correction for Single Event Upsets"
Nand Kumar and Darren Zacher, Mentor Graphics
Abstract: kumar_a.txt
Presentation: d118_kumar_s.ppt
Paper: d118_kumar_p.doc, d118_kumar_p.pdf

4:55 pm

Signal Integrity Theme

Submission 158
"Actel Compact PCI Signal Integrity"
Robert F. Hodson1, Kevin Somervill1, and Guy Gibson2
1 NASA Langley Research Center
2 Northrop Grumman
Abstract: hodson_a.doc
Presentation: d158_hodson_s.ppt

Submission 112
"Printed Circuit Board Simulation: A look at Next Generation Simulation Tools and their Correlation to Actual Laboratory Measurements"
Shahana Aziz, NASA GSFC/Northrop Grumman
Abstract: aziz_a.doc
Presentation: d112_aziz_s.ppt
Paper: d112_aziz_p.doc

5:35 pm Submission 153
"Early Output Logic and Anti-Tokens"
Charles Brej, University of Manchester
Abstract: brej_a.pdf
Presentation: d153_brej_s.ppt
Paper: d153_brej_p.pdf
6:00 pm Trivia Contest, Conference Banquet, and Panel Session: "Why Is Space Exploration So Hard? The Roles of Man and Machine"


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