Real Chip Design and Verification Using Verilog and VHDL

Ben Cohen
© 2002 by Ben Cohen
ISBN 0-9705394-2-8

1. Overview: Architectural decomposition process.
2. Fundamentals: Elements including synchronous edge detector, counter styles (e.g., Binary, One-Hot, Gray, Johnson), memories (ROM. RAM, FIFO), EDAC, cell primitives and impact on architecture, clocking schemes and PLL.
3. Synchronous/Asynchronous/Clocks/Reset: Asynchronous world, metastability, asynchronous FIFO, crossing clock domains;
4. Verification: Transaction-based verification methodology, forcing errors, counter and EDAC verification models;
5. Control Machines: Implementation methodologies with FSM and microprogrammed solutions;
6. Arithmetic Machines: HDL arithmetic operations, signed and Unsigned types.
7. Mixed Simulations and Synthesis: Mapping types, importing HDL, synthesis.
8. Minimizing Design Errors: Process, swatting bugs, recommendations.
9. Verilog /VHDL Comparisons and Guidelines: Verilog/VHDL comparison, Verilog for VHDL users, Verilog coding style guidelines.

Errata Page 134.pdf

Component Design by Example ... a Step-by-Step Process Using VHDL with UART as Vehicle

© 2001 by Ben Cohen
ISBN 0-9705394-0-1

1. Overview: Design process
2. Requirement Specification: Requirement specification template completed for UART.
3. Architectural Plan: Architectural plan template completed for UART design.
4. Verification Plan: Verification issues and template for UART verification
5. Design and Synthesis: Synthesizable UART implementation.
6. Design Verification: Verification issues and transaction based modeling with procedures and command file control.
7. Documentation and Delivery: Documentation template and UART documentation.
8. Integration of Components into Designs: Integration of UART and use of IP-Centric Synthesis Methodology
9. Reflections: Reflections of the design process

ISBN 0-7923-8115-7

©  1998 by Kluwer Academic Publishers

1. LANGUAGE ELEMENTS: Why VHDL for digital designs, salient points of concurrent statements, guarded signal assignments, configurations, arithmetic issues and operators, package std_logic_1164, range constraint in type definition, shared variables.
2. ARRAYS: Array structure representations (one dimensional, multi-dimentional), legal operations, overloaded operators on arrays, array slices and ranges, array initialization , constant arrays in case, constrained and unconstrained arrays (constraining methods, allowed constrained and unconstrained objects), mapping arrays of different sizes, unconstrained aggregate with "others ", illegal array types, unconstrained array of an unconstrained array.
3. DRIVERS: Multiple drivers (std_logic_vector solution, separate signals solution, atomicity), multiple drivers error, coding style for detection of multiple drivers.
4. SUBPROGRAMS: Side effects from a procedure, garbage collection of dynamically created objects, acceptable types in parameter lists for function calls, files declarations in procedures, multiple accesses of same file, file array, conversion function from integer to time, normalization in subprograms.
5. PACKAGES: Converting typed objects to strings, printing objects, writing to one file from multiple processes, multiple input signature register, linear feedback shift register, deferred constant, complex numbers and overloaded operators.
6. MODELS: Large ram model for simulation (traditional memory modeling, efficiency memory modeling, fixed array caching, fixed page caching, dynamic page caching, disk paging with swap files, c language interface, ram testbench and configurations), zero ohm resistor (wire, bridge) model, error injector model transfer gate (switch).
7. SYNTHESIS: supported/unsupported constructs, synthesis sensitivity rules, latch/register/combinational logic, latch inferrance in functions, variable initialization and lifetime (processes, subprograms), wait statement, shift registers, multiplexer, demultiplexer, barrel shifter, parameterized priority encoder (straight/two level encoding), generating a synchronous precharge, instantiating Synopsys DesignWare components, resource sharing, bit reversal, timer, multiplier.
8. DESIGN VERIFICATION AND TESTBENCH: Verification processes, functional verification, regression test methods (file compare, design verifier, MISR, formal verification), formal verification, bus functional model, application of misr, random, lfsr packages for auto-regression, strength stripper.
9. POTPOURRI : Methods to enhance simulation speed, accessing signals internal to components, transferring a line onto a signal, final exam (design units, compilation order, types, attributes, "wait" statement, control structure, signals versus variables, operator overloading, concurrent statements, drivers and resolution functions, subprogram).
10. DESIGN FOR REUSE: Design processes for reusability, parameterized, reusable and readable code, documentation of designs.

APPENDICES: VHDL'93 AND VHDL'87 syntax summary, Standard, TEXTIO, std_logic_1164, Std_logic_arith, predefined attributes

© 1999 by Kluwer Academic Publishers

ISBN 0-7923-8474-1

1. VHDL OVERVIEW AND CONCEPTS: Types, object classes, design units, compilation, elaboration.
2. BASIC LANGUAGE ELEMENTS: Lexical elements, syntax, operators, types and subtypes (scalar, physical, real, composite (arrays, records), access, file).
3. CONTROL STRUCTURES: Control structures and rules (if, case, loop).
4. DRIVERS: Resolution function, drivers (definition, initialization, creation ), ports
5. TIMING: Signal attributes, "wait" statement, delta time, simulation engine, modeling with delta time delays, VITAL tables, inertial / transport delay
6. ELEMENTS OF ENTITY/ARCHITECTURE: Entity, architecture, (process, concurrent signal assignment, component instantiation and port association rules , concurrent procedure, generate, concurrent assertion, block, guarded signal).
7. SUBPROGRAMS: Rules and guidelines (unconstrained arrays, interface class, initialization, implicit signal attributes, drivers, signal characteristics in procedure calls, side effects), overloading, functions (resolution function, operator overloading), concurrent procedure.
8. PACKAGES: Declaration., body, deferred Constant, "use" Clause, Signals, resolution function, subprograms, converting typed objects to strings, TEXTIO, printing objects, linear feedback shift register, random number generation compilation order
9. USER DEFINED ATTRIBUTES, SPECIFICATIONS, AND CONFIGURATIONS: Attribute declarations, attributes specifications, configuration specification and binding, configuration declaration and binding, configuration of generate statements.
10. DESIGN FOR SYNTHESIS: Constructs, register inference, combinational logic inference, state machine and design styles, arithmetic operations.
11. FUNCTIONAL MODELS AND TESTBENCHES: Testbench design methodology, BFM Modeling, scenario generation schemes, waveform generator, client/server, text command file, binary command file.
12. UART PROJECT: Architecture, transmitter, receiver, testbench, transmit/receive protocol components, transmission line, verifier, testbench, configuration.
13. VITAL: Overview, features, model, pin-to-pin delay modeling style, distributed delay modeling style.

APPENDICES: VHDL'93 AND VHDL'87 syntax, Standard, TEXTIO, std_logic_textio, std_logic_1164, numeric_std, std_logic_unsigned, std_logic_signed, std_logic_arith, std_logic_misc, predefined attributes.