PROGRAMMABLE TECHNOLOGIES WEB SITE

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

"Using Synplicity to Control Flip-Flip
Implementation for SEU-Hardness"

 

The following procedure, supplied by Synplicity, gives a procedure to synthesize code for "SEU-Hardness" and is geared for the Act 2 devices.

Either C-Mod flip-flops can be generated or TMR-triplets can be generated.  In the case of the TMR triplets, 3 C-Mod flip-flops are used and one C-Mode voter, for 7 modules per bit.  Note that Synplicity's use of the term "rad hard" for flip-flops designates a C-Mod flip-flop implementation which would properly be classified as "rad-tolerant."  Note also that there is memory (two latches) in each I/O module of Act 2 devices.  For the A1280A and RH1280 these are considered to be rad-tolerant and that the TMR technique described here do not apply to the I/O mods.   The files that Synplicity provides are user-customizable for different solutions.

 

Actel RadHard (RH1280) Usage

Introduction
There are certain cells in Actel's ACT2 library which are RadHard. RadHard (Radiation Hardened) devices are required for many military and space applications. This technical tip will describe how to utilize the RadHard features of Actel and Synplify.

How to Use Synplify 3.0b with Actel's RadHard Devices
RadHard cells are not used by default. To make your design RadHard [rad-tolerant w/ C-Mod flip-flops] using Synplify 3.0b, follow the procedure below. The procedure described is for a Verilog design. If you are using a VHDL design please read the info contained within the parenthesis ( ).

  1. When compiling the design, first include the synplcty/lib/actel/act2.v (act2.vhd) file in the Synplify project window This file contains the black_box declarations of the RADHARD cells.
  2. Add the synplcty/lib/actel/radhard_act2.v (radhard_act2.vhd) as the second file in the Synplify project window. This file has information to substitute the sequential cells (non-radhard cells) with the radhard cells. 
  3. Add your design file as the third file in the Synplify project window and click on the RUN button.

The default cells used by Synplify will be the RADHARD cells.

 

If you require TMR (Triple Module Redundancy) along with the RADHARD feature please follow the following steps.

  1. First include the synplcty/lib/actel/act2.v (act2.vhd) file as the first file in the Synplify project window. This file contains the "black_box" declarations of the RADHARD cells.
  2. Add the synplcty/lib/actel/tmr_radhard_act2.v (tmr_radhard_act2.vhd) file as the second file in the Synplify project window. This file provides the details to substitute each cell [Flip Flop/Latch] in the design with three copies of the RADHARD cell. 
  3. Add your design file as the third file in the Synplify project window and click on the RUN” button.

The result will be a radhard design with TMR. 

 

Details of what the radhard_act2.v(radhard_act2.vhd)”, tmr_radhard_act2.v (tmr_radhard_act2.vhd)”, and tmr_act2.v (tmr_act2.v) files contain:

The radhard_act2.v file has the directive:
/* synthesis syn_implement= */;

This statement tells synplify to substitue the by the RADHARD cell in that module.

The radhard_act2.vhd file has the directive:
attribute syn_implement of arch1 : architecture is "< name of synplify cell> ";

This statement tells synplify to substitue the by the RADHARD cell in that
architecture arch1.

The tmr_radhard_act2.v and tmr_act2.v file have the directives:
/* synthesis syn_preserve=1 syn_implement= */;

This substitutes each cell () by three copies of the radhard cell instantiated in that module . The synthesis syn_preserve=1” attribute tells synplify to not optimize the three registers so that the TMR is achived.

The tmr_radhard_act2.vhd and tmr_act2.vhd file and file have the directives:
attribute syn_implement of arch1 : architecture is "< name of synplify cell> ";
attribute syn_preserve of arch1 : architecture is true;

This substitutes each cell given by < name of synplify cell> with 3 copies of the radhard cell instantiated in the architecture arch1 . The attribute syn_preserve of arch1 : architecture is true” tells Synplify to not optimize the registers.

Home
Last Revised: January 09, 2002
Digital Engineering Institute
Web Grunt: Richard Katz