| HAL/S Documentation | |
|
The January/February 2006 edition of the Horizons newsletter has a number of interesting articles on open source and free software written by written by Jon Berndt. This newsletter is published by the AIAA Houston Section. |
|
|
C. Michael
Holloway |
Abstract |
|
Aerospace Report No. TOR-2004(3909)-3537 Revision B March 11, 2005 |
Foreword (excerpt) This report provides a full life cycle software development process standard based on MIL-STD-498. Additional information from EIA/IEEEE Interim Standard J-STD-016-1995, Standard for Information Technology, Software Life Cycle Processes, Software Development Acquirer-Supplier Agreement. In addition, the tailoring from Recommended Software Standards for Space Systems, Aerospace Report No. TOR-2004(3909)-3406 has been applied. |
|
Lyndon B. Johnson Space Center |
Abstract |
|
Jack Garman |
Introduction (excerpts) Discussion of the software problem which delayed the first Shuttle orbital flight. On April 10, 1981, about 20 minutes prior to the scheduled launching of the first flight of America's Space Transportation System, astronauts and technicians attempted to initialize the software system which "backs-up" the quad-redundant primary software system ......and could not. In fact, there was no possible way, it turns out, that the BFS (Backup Flight Control System) in the firth onboard computer could have been initialized properly with the PASS (Primary Avionics Software System) already executing in the other four computers. |
|
|
Norfolk, Virginia |
|
Communications of the ACM, December 1985, Volume 28, Number 12. Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the publication and its date appear. and notice is given that copying is by permission of the Association for Computing Machinery. To copy otherwise or to republish. requires a fee and/or specific permission. |
Note: While some of this paper is specific to the SDI system back in
the 1980's, a good amount of the engineering analysis is applicable to those
who wish to treat the digital logic design problem as a software task and
use software methods. This analysis is applicable to our work today.
-- rk Summary:
|
|
S. Goldberg, M. Maimone, L. Matthies |
Abstract |
|
|
Inhalt Programmfehler sind oft nur irritierend, können aber auch verheerende Folgen haben. Ein Fehler im Pentium-Prozessor kostete Intel im Jahr 1994 US$ 306 Millionen. Fehler in einem Steuerrechner des neuen Stellwerks im Bahnhof Hamburg Altona führten im Jahr 1995 dazu, daß der Bahnhof für mehrere Tage nicht angefahren werden konnte, und verursachte erheblichen Ärger bei den Bahnkunden. Aus der Luft- und Raumfahrt sind etliche durch Softwarefehler verursachte Unfälle bekannt, die zum Teil auch zum Verlust von Menschenleben führten. In dem Proseminar wollen wir einige der bekanntesten dieser Fehler und die durch sie ausgelösten Desaster untersuchen. Dabei soll jeweils
|
|
Eslinger, S. The Aerospace Corporation |
Purpose and Scope The purpose of this white paper is to address the issues raised in the recently published Senate Armed Services Committee Report 106-50 concerning Software Management Improvements for the Department of Defense (DoD). The text, titled "Software Management Improvements," extracted from Title VIII (Acquisition Policy, Acquisition Management, and Related Issues) of Senate Report 106-50, is given for reference in Table 1-1 of the body of this report. This paper recommends a set of software acquisition and software engineering best practices that addresses the issues raised in the Senate Report. These recommendations are based upon the experience of The Aerospace Corporation in supporting the United States Air Force (USAF) and the National Reconnaissance Office (NRO) in the acquisition of DoD space systems. The domain of application of the recommended best practices, therefore, is the acquisition and development of large software-intensive, mission-critical systems, such as space systems, which are for the most part unprecedented. |
|
NASA Public Lessons Learned System (PLLS) Database |
Abstract: Shortly after the commencement of science activities on Mars, an MER rover lost the ability to execute any task that requested memory from the flight computer. The cause was incorrect configuration parameters in two operating system software modules that control the storage of files in system memory and flash memory. Seven recommendations cover enforcing design guidelines for COTS software, verifying assumptions about software behavior, maintaining a list of lower priority action items, testing flight software internal functions, creating a comprehensive suite of tests and automated analysis tools, providing downlinked data on system resources, and avoiding the problematic file system and complex directory structure. |
|
Introduction Logic designers often replicate logic for reliability or performance reasons. For example, if the load on an output is too high, then the load will often be split between multiple drivers (in some cases outputs may be joined together but this is not preferred and is usually avoidable). In other cases, cutting the load and duplicating the driver can help make timing by distributing the capacitive load. The replication of combinational logic is quite straightforward. However, if this concept is extended to sequential logic then the situation is trickier since state information is involved. Indeed, the logic may present different information to different parts of the circuit and, for example, may be inconsistent in the presence of a trasient fault such as a single event upset, ESD event, etc. That is, the logical flip-flop can present different values to different parts of the circuit depending on which physical flip-flop they connected to. This is a call for caution in high-reliability applications. Software CAE tools are more than happy to generate circuits of this class and do not generate logic to ensure self-consistency. |
|
Fred Martin, MIT/IL |
Introduction 25 years ago it happened, the first Lunar Landing, Apollo 11 - July 20,1969. It was an exciting, exhilarating time of total focus and dedication. Current and alumni Intermetrics employees were intimately involved with the project since its inception in 1960 (John Miller, Jim Miller, Ed Copps, Jim Flanders, Dan Lickly, Joe Saponaro, Bill Widnall, John Green, Alex Kosmala, Ray Morth, Steve Copps and me, Fred Martin). The most memorable part of the flight for me, aside from the landing and the moonwalk itself, was the descent from lunar orbit to the surface. I'd like to present a personal remembrance and perspective. |
ESA Software Initiative May 7, 2003 |
Why the ESA Software Initiative
|
Nancy G. Leveson1 and Clark S. Turner2 |
Introduction Computers are increasingly being introduced into safety-critical systems and, as a consequence, have been involved in accidents. Some of the most widely cited software-related accidents in safety-critical systems involved a computerized therapy machine called the Therac-25. Between June 1985 and January 1987, six known accidents involved massive overdoses by the Therac-25 -- with resultant deaths and serious injuries. They have been described as the worst series of radiation accidents in the 35-year history of medical accelerators. |
Minimizing HDL Design Errors Ben Cohen Minimizing_Design_Errors_HDL.pdf |
Abstract This paper discusses processes, methodologies, and classes of tools necessary to minimize ASIC and FPGA design errors. (added July 5, 2001) |
| VHDL
Modelling Guidelines
european space research and technology centre
ASIC/001, Issue 1 |
Abstract This document defines requirements on VHDL models and testbenches, and is intended to be used as an applicable document for ESA developments involving VHDL modelling. It is mainly focused on digital models; specific requirements for analog modelling have not been covered. The requirements concern simulation and documentation aspects of VHDL models delivered to ESA; specific rules and guidelines for logic synthesis from VHDL have not been included. Nevertheless, the requirements of this document are compatible with the use of logic synthesis. The requirements are not applicable for the case when a design database is transferred in VHDL format. The purpose of these requirements is to ensure a high quality of the developed VHDL models, so they can be efficiently used and maintained with a low effort throughout the full life-cycle of the modelled hardware. The requirements are based on the VHDL-93 standard, to minimise future maintenance efforts for updating models. However, in an initial stage the models shall be backward compatible with VHDL-87 as far as possible, since some tools will not be updated immediately. The requirements have been structured in a general part applicable to all VHDL models, and additional requirements applicable to different kinds of models. In addition, VHDL code examples and a list of common problems encountered have been included in order to provide some guidance to the VHDL developer. If not stated which kind of model is to be developed, the default kind is a model for Component simulation. (Added March 20, 2001) |
| Force_Errors.pdf | Forcing Signal Errors with VHDL Abstract This paper presents a technique, which uses the user-defined resolution function feature of VHDL, to selectively control from VHDL the assertion of errors imposed on testbench signals of type Std_Logic. This technique allows the testbench environment to selectively inject errors at specific times and with specific values onto signals to verify the design-under-test responses to interface errors. (January 4, 2001) |
| EDAC8Cyclic.pdf edac.vhd edac_rtl.vhd edac_tb.vhd |
A (16,8) Error Correcting Code (T=2) For Critical Memory
Applications Abstract High density SRAMs generate errors in their stored data because of natural radiation. This is a particular problem for computing on-board a satellite , where the single-error correction of the usual Hamming code can be inadequate. The two-bit error correcting code described here is a more powerful and efficient alternative. (12/21/2000) |
| Component_Verification.pdf | Component Verification by Example Abstract This paper presents, by example, some of the key features of the front-end processes for specifying the planning of both the implementation and verification (i.e., testbench) of a design to ensure that the implemented design meets its intended requirements and costs. (12/19/2000) |
| R1-2000_Installation.htm | Designer R1-2000 - Installation Notes. A DCOM update is required for some Microsoft OS installations. (Dec. 11, 2000). |
| DesignerVariables.htm | Variables for Designer Software - Placement and Routing (December 8, 2000). |
| Combiner.htm | How to Read Combiner Information Files |
| LEON-1 VHDL model | The LEON core is a SPARC* compatible integer unit developed
for future space missions. It has been implemented as a highly configurable, synthesisable
VHDL model. To promote the SPARC standard and enable development of system-on-a-chip (SOC)
devices using SPARC cores, the European Space Agency is making the full source code freely
available under the GNU LGPL license. The LEON-1 processor should be seen as a demonstrator of the LEON core. As such, it implements a minimum of interfaces and functions. Once the LEON core has been fully verified, a more complete processor (LEON-2) will be developed with functions such as PCI interface, floating-point unit and DRAM controller. The LEON core has been extensively tested against the IEEE-P1754 (SPARC) standard, but have not been formaly tested and cerified by SPARC international as being SPARC V8 compliant. |
| ESA_DesignReq.pdf | ASIC Design and Manufacturing Requirements - ESA |
| VHDL87_Syntax.htm | VHDL '87 Syntax Diagrams. |
| VHDL93_Syntax.htm | VHDL '93 Syntax Diagrams |
| synopsis_actel.pdf | "Using Synopsis to Design Actel's Radiation-Hardened
FPGAs," Abstract This application note shows how to use Synopsis automation scripts to control synthesis such that SEU soft flip-flops (S-Module flip-flops) are excluded from the synthesized output. The synthesis can be controlled to either use radiation-tolerant flip-flops (C-Module or C-C flip-flops) or triple-modular redundant (TMR) structures. (.pdf 39 kbytes) |
| SynplicitySEUControl.htm | "Using Synplicity to Control Flip-Flip Implementation for
SEU-Hardness" Abstract A procedure is given and discussed on now to use Synplicity to control the flip-flop implementation. Either C-Mod flip-flops or TMR implementations are generated from VHDL or Verilog HDL code. |
| ACTmap_ForLoop.PDF | "VHDL Coding Style in ACTmap" Abstract As we move to a higher percentage of design using VHDL, it is important to understand the effects of VHDL on design efficiency and device performance. A number of tests using different coding styles have been run. |
| VL_74_R@1998_Upgrade.htm | "Updating from WVOffice 7.31 and Designer 3.1.1u1 to WVOffice 7.4 and Designer R2-98 on a PC" |
| AsynchronousLoops.htm | Procedure for having Designer software detect asynchronous feedback loops in timing analysis. |
| HoldTimeCalculation.PDF | Note on clock skew not in calculations for Designer software, 3.0 and later. (.pdf 28 kbytes). |
| Converting Objectstore Databases | Converting Designer 3.0 and 3.1 Objectstore databases to the new format. |
| Programming with Old Actel Databases | Which versions of Actel software can program the .def and .fus file formats and how do I convert files to the .afm file format for new versions of the software? |
| Actel Database Compatibility | App note on Actel database compatibility across platforms |
| VHDL and Other References | List of VHDL Books, Documents, and Reports and some other references. |
| Actgen R3-1998 Patch | Actgen Patch for R3-1998 Designer Software - Certain taps in LFSR are incorrect. |
| Actgen R3-1998 Bug Inverted Output | Actgen Bug for R3-1998 Designer Software - in modulo-class counters, the output may be inverted. Additionally, counts should be verified. |
| Safe State Machines with Synplify | "Designing Safe VHDL State Machines with Synplify". Discussion of Synplicity mechanism for handling the VHDL problem of trap states. Posted 8/15/99 (Version 5.1.5a current). |
LFSR Testbench |
The LFSR testbench can help you understand the LFSR basics:
Courtesy of Jean Nicolle (http://www.logiccell.com/~jean/LFSR/) |
| Unix2DosZip.EXE | Unix to DOS file conversion package that runs under Windows. |
| KPP.htm | KPP - a pre-processor, similar to CPP, for VHDL applications. It provides many standard functions such as #def, #undef, #ifdef, #include, etc. It also provides for loops and some other features. The program will run on Win '95, Win '98, and Win NT. For this version, use the default directory for installation. |
| Arithmetic Module Generator for High Performance VLSI Designs | Enter parameters and it outputs VHDL for adders, subtractors, multipliers,
and squarer. Link to: Norwegian University of Science and Technology |
WWW Site |
Technology Description |
Technical Contact |
| Intellitech | Intellitech Corporation develops Intellectual Property (IP) for efficient configuration, debug and test of electronic products including SoC (System-on-a-Chip), ICs, PCBs and Systems. The IP provides a scalable configuration, debug, and test infrastructure that enables self-testable and in-the-field re-configurable products. | Bret O. Moses Intellitech Corporation 229 Polaris Ave., Suite 7 Mountain View, CA 94043 Tel: 650-968-4784 Cell: 408-394-5003 bmoses@intellitech.com |
| Microelectronics: VHDL | ESA Synthesizable VHDL Models The VHSIC Hardware Description Language (VHDL) is a formal notation intended for use in
all phases of the creation of electronic systems. The European Space Very high integration levels of microelectronics will be required to fulfil the ever-increasing demands for high processing performance, low mass and power. With an increasing number of available gates on silicon, the functionality being implemented will move away from the use of traditional components to more advanced and complex systems within a single device. To develop such complex circuits the design methodology will have to change from being gate-level oriented to the integration of complex building blocks. The designers will have to rely on pre-existing building blocks with already verified functionality, with documentation and production test vectors being available, and which have ultimately been validated on silicon. The contents of this page is related to VHDL building blocks for microelectronic developed in the scope of European Space Agency (ESA) activities, ranging from in-house developments to contractor work and from simple Field Programmable Gate Arrays (FPGA) to complex System-On-a-Chip (SOC) devices. |
Martin.Hollreiser@esa.int |
| Welcome | The purpose of this web site is to explain and promote the design and implementation of FPGA-based CPUs and integrated systems-on-a-chip. | Gray Research LLC P.O. Box 6156 Bellevue, WA 98008-1156 USA Tel: (425) 861-8781 xsoc@fpgacpu.org |
| Mentor Graphics Corporation | CAE Vendor Inventra IP for Actel |
|
| Model Technology | ModelSim VHDL, Verilog, and Mixed-HDL Simulator | Tel: (503) 641-1340 Fax: (503) 526-5410 support@model.com Model Technology, Inc. 8905 SW Nimbus Ave., Suite 150 Beaverton, Oregon 97008-7159 |
| StateCAD | Translates Graphical State Machines to HDL | support@statecad.com Tel: (954) 423-8448 Fax: (954) 423-8434 |
| Synopsys Home Page | ||
| Synplicity: Home Page | support@synplicity.com Tel: (408) 617-6000 |
|
| Viewlogic Systems Group | http://www.viewlogic.com/support/index.html pc-support@viewlogic.com |
|
| The Free IP Project | The Free-IP project is an effort to make quality IP available
to anyone. What is IP? IP is short for Intellectual Property. More specifically, it is a block of logic that can be used in making ASIC's and FPGA's. Examples of "IP Cores" are, UART's, CPU's, Ethernet Controllers, PCI Interfaces, etc. In the past, quality cores of this nature could cost anywhere from US$5,000 to more than US$350,000. This is way too high for the average company or individual to even contemplate using-- Hence, the Free-IP project. Initially the Free-IP project will focus on the more complex cores, like CPU's and Ethernet controllers. Less complex cores might follow. |
David Kessner |
Home - NASA
Office of Logic Design
Last Revised:
August 08, 2007
Digital Engineering Institute
Web Grunt: Richard
Katz
