NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

IP Library

Here is some IP that has been contributed or collected from the public domain.   These are posted as an aid, to myself and for others, and you should ensure that they are correct.  I am not verifying all of them.  Of course, please report any problems or suggestions that you have and we'll get them fixed.  And, naturally, feel free to make your own contributions.

Function	VHDL	Verilog
Binary to Gray		bin2gray.v1
Gray to Binary		gray2bin.v1
Gray Counter		gray_cntr.v1 gray_counter.v1
Up/Down Gray Counter		gray_updown.v1
Johnson Counter		johnson_counter.v1
Johnson Decoder		johnson_decode.v1
Up/Down Johnson Counter		johnson_ud.v1
LFSR Counter, many-to-one		lfsr_mto.v1
LFSR Counter, one-to-many		lfsr_otm.v1
Ring Counter		ring.v1
Ring Counter, BCD		ring_bcd4.v1

Contributor:
¹  Dan Elftman, Actel Corporation

 

HT-Labs Cores

CPU86 8088/8086 FPGA IP Core From Hans Tiggeler's HT-Labs	On this page you will find a free FPGA IP Core implementation of an 8088/8086 processor. The CPU86 core is fully binary/instruction compatible with an 8086/8088 processor, it is however not cycle and timing accurate. The CPU86 core consist of an 8 bits Bus Interface Unit, an 8086 Processor Core and a Hardware Debug Unit. The debug unit is used to interrogate the internal registers during single stepping. The output of the debug unit is written in a DOS "debug.exe" style format to a build-in fixed format UART. The simulation model comes with a simple testbench instantiating the CPU86 core together with a 256Byte ROM model, a 16KByte SRAM model, two UARTs, a simple I/O Port (PIO) and a Real Time Clock (RTC). All perhipherals are basic but synthesizable. The SRAM model is pre-loaded with the MON88 debugger and the ROM contains a simple "Jump to MON88 after reset" program. The testbench monitors the UART and copies any CR terminated strings to the Modelsim transcript window, it also contains a simple function to transmit command string to the UART.
AES86, a 128 Bit AES ECB/CBC IP Core From Hans Tiggeler's HT-Labs	Summary AES86 is a VHDL implementation of the Rijndael encryption algorithm. This algorithm was approved by the US National Institute of Standards and Technology (NIST) as the new cryptographic (derived from the Greek word Kryptos which means to hide)  algorithm to protect sensitive unclassified information for the US government. Due to the simplicity and strength of the Rijndael algorithm it is now used in encryption applications worldwide. The Rijndael algorithm was developed by the Belgium Dr. Joan Daemon and Dr. Vincent Rijmen. The AES core on this page is implemented as a coprocessor for an 8 bits microcontroller and supports both the ECB and CBC mode.
RCORE54 Processor From Hans Tiggeler's HT-Labs	Summary Small 33 instruction RISC processor with a build-in UART   A small microprocessor design called “Rcore54” implemented using Mentor Graphics HDL_Designer, Modelsim PE/SE and Leonardo Spectrum. The core is binary compatible with Microchip’s PIC16C52/54 microcontroller.
Serial Signed/Unsigned Multiplier + Testbench From Hans Tiggeler's HT-Labs	Note: for RTL designs it is advisable to use the '*' operator which will result in an optimised target FPGA multiplier. As far as I know no synthesis tool will infer a optimised multiplier from the Parallel Radix-4 design.
Parallel Signed/Unsigned Radix-4 Multiplier + Testbench From Hans Tiggeler's HT-Labs	Note: for RTL designs it is advisable to use the '*' operator which will result in an optimised target FPGA multiplier. As far as I know no synthesis tool will infer a optimised multiplier from the Parallel Radix-4 design.
Serial Signed/Unsigned Divider + Testbench From Hans Tiggeler's HT-Labs
Parallel Signed/Unsiged Divider + Testbench From Hans Tiggeler's HT-Labs

 

Processors

GRFPU High-Performance Floating-Point Unit http://www.gaisler.com/fpu.htmlXL	Introduction The GRFPU is an IEEE-754 compliant floating-point unit, supporting both single and double precision operands. The advanced design combines high throughput with low latency, providing up to 250 MFLOPS on a 0.18 um ASIC process. The host interface is clean and versatile, simplifying the interfacing to processor pipelines and DSPs. The accuracy and convergence of the FPU algorithms have been proven mathematically, and the implementation has been validated with more than 20 million test vectors.
HC11 Core GM HC11 CPU Core http://www.gmvhdl.com/hc11core.htmlXL	Summary The HC11 CPU Core is a fully-synthesizable VHDL implementation of the HC11 CPU. All instructions are currently implemented with the exception of the divide instructions. The GM HC11 CPU Core package includes the synthesizable core, projects, self-checking testbenches and a debugger.
Project: RISC5x http://www.opencores.org/projects/risc5x/XL	Summary A small RISC CPU (written in VHDL) that is compatible with the 12 bit opcode PIC family. Single cycle operation normally, two cycles when the program counter is modified. Clock speeds of over 40Mhz are possible when using the Xilinx Virtex optimisations.

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Last Revised: January 22, 2006
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