module ring(Q, Co, Init, Ci, Clk);
parameter WIDTH = 5;
output [WIDTH-1:0] Q;
output Co;
input Init, Ci, Clk;

reg [WIDTH-1:0] Q;

always @(posedge Clk or negedge Init)
 if (Init==1'b0) begin
   Q <= 1;
 end
 else begin
  if (Ci==1'b1)  
   Q <= {Q[WIDTH-2:0],Q[WIDTH-1]};
 end
assign Co = Q[WIDTH-1] && Ci;
endmodule