`timescale 1ns/100ps module LFSR_MTO(Q,CLK,RST_L,ENAn); parameter WIDTH = 4, RETURN_TO_ZERO = 1; output [WIDTH - 1:0] Q; reg [WIDTH - 1:0] Q; input CLK,RST_L,ENAn; parameter Tco = 2; /* -- N Bit LFSR with for 2**n-1 states, initial value must be 4'b0001. -- -- This one-to-many LFSR with zero modification for 2^N states can be -- modified to operate in any of the following modes: -- -- Bits Taps Bits Taps Bits Taps -- ----------------------------------------------------------------------- -- 2.......[0,1] 13......[0,2,3,12] 23......[4,22] -- 3.......[0,2] 14......[0,2,4,13] 24......[0,2,3,23] -- 4.......[0,3] 15......[0,14] 25......[2,24] -- 5.......[1,4] 16......[1,2,4,15] 26......[0,1,5,25] -- 6.......[0,5] 17......[2,16] 27......[0,1,4,26] -- 7.......[0,6] 18......[6,17] 28......[2,27] -- 8.......[1,2,3,7] 19......[0,1,4,18] 29......[1,28] -- 9.......[3,8] 20......[2,19] 30......[0,3,5,29] -- 10......[2,9] 21......[1,20] 31......[2,30] -- 11......[1,10] 22......[0,21] 32......[1,5,6,31] -- 12......[0,3,5,11] -- */ reg [32:0] taps; reg feedback; integer i; always @(posedge CLK or negedge RST_L) if (RST_L==1'b0) begin // // If the Return to Zero option is set the counter resets // to the all 0 state, otherwise it gets set to 1 and the // all 0 state is an illegal state // if (RETURN_TO_ZERO) Q = 0; else Q = 1; end else if (ENAn==1'b0) begin // // The following case statement on a constant parameter // will not produce any logic it simplifies the tap selection // for the user who only needs to specify the width of the LFSR // counter // case (WIDTH) 2: taps = 2'b11; //[0,1] 3: taps = 3'b101; //[0,2] 4: taps = 4'b1001; //[0,3] 5: taps = 5'b1_0010; //[1,4] 6: taps = 6'b10_0001; //[0,5] 7: taps = 7'b100_0001; //[0,6] 8: taps = 8'b1000_1110; //[1,2,3,7] from HDL Chip Design 9: taps = 9'b1_0000_1000; //[3,8] 10: taps = 10'b10_0000_0100; //[2,9] 11: taps = 11'b100_0000_0010; //[1,10] 12: taps = 12'b1000_0010_1001; //[0,3,5,11] 13: taps = 13'b1_0000_0000_1101; //[0,2,3,12] 14: taps = 14'b10_0000_0001_0101; //[0,2,4,12] 15: taps = 15'b100_0000_0000_0001; //[0,14] 16: taps = 16'b1000_0000_0001_0110; //[1,2,4,15] 17: taps = 17'b1_0000_0000_0000_0100; //[2,16] 18: taps = 18'b10_0000_0000_0100_0000; //[6,17] 19: taps = 19'b100_0000_0000_0001_0011; //[0,1,4,18] 20: taps = 20'b1000_0000_0000_0000_0100; //[2,19] 21: taps = 21'b1_0000_0000_0000_0000_0010; //[1,20] 22: taps = 22'b10_0000_0000_0000_0000_0001; //[0,21] 23: taps = 23'b100_0000_0000_0000_0001_0000; //[4,22] 24: taps = 24'b1000_0000_0000_0000_0000_1101; //[0,2,3,23] 25: taps = 25'b1_0000_0000_0000_0000_0000_0100; //[2,24] 26: taps = 26'b10_0000_0000_0000_0000_0010_0011; //[0,1,5,25] 27: taps = 27'b100_0000_0000_0000_0000_0001_0011; //[0,1,4,26] 28: taps = 28'b1000_0000_0000_0000_0000_0000_0100; //[2,27] 29: taps = 29'b1_0000_0000_0000_0000_0000_0000_0010; //[1,28] 30: taps = 30'b10_0000_0000_0000_0000_0000_0010_1001; //[0,3,5,29] 31: taps = 31'b100_0000_0000_0000_0000_0000_0000_0100; //[2,30] 32: taps = 32'b1000_0000_0000_0000_0000_0000_0110_0010; //[1,5,6,31] endcase // // If the Return to zero option is set then the feedback term is set to the // reduction NOR function of the MSB-1 down to LSB. In english, the // feedback term is set to '1' when all of the bits other than the // MSB(which is a don't care) are '0'. // // In the Return to one mode, the feedback term simply gets initialized // to '0' // if (RETURN_TO_ZERO) feedback = ~|Q[WIDTH - 2:0]; else feedback = 1'b0; // // XOR the bits selected in the taps register for feedback to the LSB // for ( i = 0; i <= WIDTH - 1; i = i + 1) if (taps[i]==1'b1) feedback = feedback ^ Q[i]; // // Shift Q one bit to the left // Q = Q<<1; // // LSB gets the feedback XOR result // Q[0] = feedback; end endmodule