`timescale 1ns/100ps 
module johnson_ud (clk, aclr, ena, up, johnson_code);
 parameter Width = 4;
 input clk, aclr, ena, up;
 output [Width-1:0] johnson_code;

 reg [Width-1:0] johnson_code;
 
 always @(posedge clk or negedge aclr) 
  if (aclr==1'b0) begin
   johnson_code <= 0;
  end
  else begin
  if (ena==1'b1) begin
   if (up==1'b1) 
    johnson_code <= {johnson_code[Width-2:0],!(johnson_code[Width-1])};
   else
    johnson_code <= {!johnson_code[0],johnson_code[Width-1:1]};
  end //enabled
 end //sequential update
endmodule