`timescale 1ns/100ps 
module gray_updown (clk, aclr, ena, up, gray_code);
 parameter SIZE = 22;
 input clk, aclr, ena, up;
 output [SIZE-1:0] gray_code;
 reg [SIZE-1:0] gray_code,tog;
 integer i,j,k;
 always @(posedge clk or negedge aclr) 
  if (aclr==1'b0) begin
   gray_code <= 0;
  end
  else begin //sequential update
  if (ena==1'b1) begin //enabled
   tog = 0;
   for (i=0; i<=SIZE-1; i=i+1) begin  //i loop
    //
    // Toggle bit if number of bits set in [SIZE-1:i] is even
    // XNOR current bit up to MSB bit for Count Up, and
    // XOR for Count Down
    //
    for (j=i; j<=SIZE-1; j=j+1) tog[i] = tog[i] ^ gray_code[j];  
    if (up==1'b1) tog[i] = !tog[i];                 
    //
    // Disable tog[i] if a lower bit is toggling
    //
    for (k=0; k<=i-1; k=k+1) tog[i] = tog[i] && !tog[k];
   end //i loop
   //
   //Toggle MSB if no lower bits set (covers code wrap case)
   //
   if (tog[SIZE-2:0]==0) tog[SIZE-1] = 1; 
   //
   //Apply the toggle mask
   //
   gray_code <= gray_code ^ tog;          
  end //enabled
 end //sequential update
endmodule