`timescale 1ns/100ps
module graycntr (gray, clk, inc, rst_n);
parameter SIZE = 12;
output [SIZE-1:0] gray;
input clk, inc, rst_n;
reg [SIZE-1:0] gnext, gray, bnext, bin;
integer i;

always @(posedge clk or negedge rst_n)
 if (!rst_n) gray <= 0;
// else if (inc) gray <= gnext;
 else gray <= gnext;

always @(gray or inc) begin
 for (i=0; i<SIZE; i=i+1) bin[i] = ^(gray>>i); //Gray2Bin
 bnext = bin + inc;                            //Increment
 gnext = (bnext>>1) ^ bnext;                   //Bin2Gray
end

endmodule