UTMC has identified the following anomaly in the power up behavior of the UT22VP10 RADPAL (RC01 and RC02).

The anomaly was observed for a power-up application where a residual voltage between 300 and 500 mV was supplied to the VDD pin(s) of the RADPAL forseveral milliseconds prior to the 5V power supply ramping to 5 volts.   Consequently, the RADPAL enters a "test" mode (as opposed to a "user" mode).  In the test mode, all output buffers are placed and remain in a high impedance state and the RADPAL does not function as programmed.  Through HSPICE simulation and laboratory tests, UTMC has found there exists a window in which a residual voltage of a few hundred millivolts on the VDD pin(s) prevents the RADPAL from generating an internal POR signal for its security circuit. The lack of a reset signal allows the security circuit to power up in either the "user" or the "test" mode of operation. Entering the "test" mode prevents the RADPAL from functioning as programmed. The anomaly is seen at temperatures above 25 °C in combination with a residual voltage, above 300mV, applied to VDD before it transitions monotonically to VDD minimum. The anomaly is not seen when the application of power to the RADPAL starts at zero volts and transitions monotonically to VDD minimum and the slew rate is greater than 0.1V/S.  The anomaly is not wafer lot dependent and affects all date code shipped.

The UT22VP10 RADPAL is susceptible to this POR anomaly whenever residual voltages of between 300mV and 500mV are on the VDD pin(s) prior to the application of the 5V power supply In order to avoid powering up the UT22VP10 RADPAL in a test mode, the following specifications must be met:

1. The application of voltages on the VDD pin(s) of the RADPAL must start at 0V and reach 1V at a rate of 0.1V/s or faster.
2. The power-up voltage must be continuously increasing with respect to time, through 3V, and monotonic thereafter.
3. No voltage can be applied to VDD prior to the intended power-up sequence.