DATE: November 6, 2002
Here is the sixth in a series of OLD News articles.
In FPGAs, flip-flops normally are implemented via dedicated registers, hard-wired into the devices. However, flip-flops can also be implemented via logic macros with feedback. These types of flip-flops are supported by Actel and offer two advantages:
- Increased SEU tolerance
- Additional flip-flop resources
As described by the vendor in the Macro Library Guide, July 2000 as applying to ACT 2/1200XL, ACT 3, 3200DX, 42MX, 54SX, 54SX-A, and eX technologies.
CC-Module Flip Flops
These macros are useful in some radiation hostile applications. They sacrifice area in exchange for a lower single-event upset (SEU) rate caused by ion particle collisions. These special cells use two combinational modules to implement a register instead of using the dedicated registers in the array. (See the application note titled, Design Techniques for RadHard Field Programmable Gate Arrays.)However, it was found that in SX, SX-A, and SX-S the storage elements for some of the hard macros were implemented as R-Cells. I did not try eX devices. The impact for SX-S devices will be a potential decrease in the number of flip-flops available. For SX and SX-A devices, there will be the additional impact of lower then expected SEU tolerance. This is not obvious but can be deduced by looking at reports and the chip's layout. The newer library guides have been updated to reflect the performance of the CAE software.
A detailed discussion of this, with examples and techniques for evaluating the hardware and the impact to SEU tolerance, has been written up as an application note.
In my new OLD (Office of Logic Design) position, I am now making some of my informal e-mail lists semi-formal. These mailings will have pointers to tech tips that can [hopefully] proactively prevent errors from getting into flight designs or make things go faster and smoother. I have included an array of people from a number of number of organizations; different NASA Centers, ESA, etc., as you all may distribute to people in your own organizations and other colleagues. Please let me know if you are on this list in error or if someone should be added to it. This list is targeted towards those that either will design or review space flight digital electronics. Feel free to suggest topics for discussion and research or to contribute news items. [Note for this web-based release: to become a recipient on this mailing list, please send e-mail to: richard.b.katz@nasa.gov.]
All application notes are uploaded onto my www site. New additions are noted on the what's new page. I will give these mailings from time to time; too much and they will be filtered and ignored - too little and not enough information flows. So I'll try and hit a good balance.
Best regards,
-- rk
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