NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

OLD News #3

OLD News #3: Input Transition Times for SX-S FPGAs

DATE: June 24, 2002

Here is the third in a series of OLD News articles.

For Actel FPGAs, the input transition time specification has been tightened over the years. Originally, Act 1, Act 2, and Act 3 FPGAs had a specification of 500 ns, when measured between 10% and 90% of the input signal. The RT54SX series devices had a specification of 50 ns. The more recent RT54SXS series devices dropped this parameter to 10 ns.

There are two issues if one fails to meet this specification:

1. A malfunction from multiple transitions, as the input circuit may glitch at the transition point.
2. Long-term reliability (i.e., electromigration).

For a 10 ns transition time, typical circuits such as pull-up or pull-down circuits can not be made to work in practice. Also, interfacing outputs of devices such as 54HCxx to a RT54SXS input often can not pass a worst-case analysis.

Actel has recently produced a report that states that the device will not be damaged if the input transition time specification is not met.

rtsxs_trtf_report_final.pdf

However, the 10 ns specification time has not been relaxed for reliable, functional operation.  There are a number of techniques such as bus hold circuits, state machine solutions, etc., for applying these devices and having them operate reliably.

For additional reading on this topic, please see:

C_Input_Stages.ppt

EEE_Links_Nov00.pdf (section titled: Input Transition Times)

input_transition_time.htm

sx-a_sx-s_input_slew_rates.htm

In my new OLD (Office of Logic Design) position, I am now making some of my informal e-mail lists semi-formal. These mailings will have pointers to tech tips that can [hopefully] proactively prevent errors from getting into flight designs or make things go faster and smoother. I have included an array of people from a number of organizations; different NASA Centers, ESA, etc., as you all may distribute to people in your own organizations and other colleagues. Please let me know if you are on this list in error or if someone should be added to it. This list is targeted towards those that either will design or review space flight digital electronics. Feel free to suggest topics for discussion and research or to contribute news items.  [Note for this web-based release: to become a recipient on this mailing list, please send e-mail to: richard.b.katz@nasa.gov.]

All application notes are uploaded onto my www site. New additions are noted on the what's new page. I will give these mailings from time to time; too much and they will be filtered and ignored - too little and not enough information flows. So I'll try and hit a good balance.

whats_new.htm

Best regards,

-- rk

Home - NASA Office of Logic Design
Last Revised: January 25, 2005
Digital Engineering Institute
Web Grunt: Richard Katz