NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

OLD News #16

Testing of Actel SX-A and RTSX-S Programming Algorithms

 

Update: June 29, 2004.  Added early NASA Phase 0 test results, LTOL data for the RT54SX72S

Update: June 21, 2004: Added testing of 300 RT54SX32SU (0.25 µm UMC) devices to the test matrix.

Update: June 15, 2004.  Updated the number of test hours.

Update: May 20, 2004.  Added data on RT54SX72S.

Date: May 17, 2004

This is the sixteenth in a series of OLD News articles.

 

Synopsis

OLD News #15 discussed the eleven confirmed programmed antifuse failures in the SX-A and RTSX-S series Actel FPGAs, built in the 0.25 µm MEC/Tonami process and were either programmed with hardware that subsequently failed calibration, or operated in an out-of-specification or unknown electrical environment.  No programmed antifuse failures have been reported with 0.22 µm SX-A or eX series devices.

Actel Corporation has developed a new programming algorithm for the SX-A and RTSX-S devices built in the 0.25 µm MEC/Tonami process, scheduled for release in May, 2004.  Their internal testing and qualification effort has, to date, produced no detected failures in over 800 devices.  It is noted that devices programmed with the old programming algorithm and subjected to the same electrical environment, failed at a rate of approximately 2.5%.

An "Industry Tiger Team," led by The Aerospace Corporation, will evaluate RTSX-S series devices programmed with the old algorithm.  This approach is dictated by Aerospace Corporation management and is based on certain programs' desire to rationalize using existing hardware "as is."

In light of the above, the NASA Office of Logic Design will evaluate RTSX-S series devices programmed with Actel's new algorithm as well as RTSX-SU series FPGAs.  This independent NASA activity is endorsed and sponsored by the NASA Engineering and Safety Center.

 

Discussion

Performance Comparison of Old vs. New Programming Algorithms, A54SX72A-PQ208 (Actel internal)

A comparative evaluation of old and new algorithms has been made by subjecting devices to a "dirty burn-in"  test.  A dirty burn-in environment is defined as a set of operating conditions in violation of the manufacturer's specification.  Specifically, these conditions are as follows:

The results with old programming algorithm are as follows:

The results for the new programming algorithm are as follows, at the time of this writing.  Note that the tests are cumulative, with 705 devices total in test, with different batches started at different times.

 

Testing of RTSX-S Series Devices  Programmed with the New Algorithm (Actel internal)

RT54SX32S

RT54SX72S

 

NASA Independent Test and Evaluation

An "Industry Tiger Team," led by The Aerospace Corporation, will evaluate RTSX-S series devices programmed with the old algorithm.  This approach is dictated by Aerospace Corporation management and based on certain programs' desire to rationalize using existing hardware "as is."  In light of this, the NASA Office of Logic Design will evaluate RTSX-S series devices programmed with the Actel's new algorithm and RTSX-SU devices.  This independent NASA activity is endorsed and sponsored by the NASA Engineering and Safety Center.  The test protocol will follow that of the "Industry Tiger Team" with 300 RT54SX32S-CQ208 devices tested, all configured with the new programming algorithm, along with 300 RT54SX32SU-CQ208 units.  Aerospace Corporation-led testing will comprise 1,150 devices of the same type, all configured with the old programming algorithm.  Both NASA OLD and Aerospace Corporation test environments will be even harsher than Actel's "dirty burn-in" test conditions, with electrical stress applied via simultaneous switching outputs, simultaneous switching undershoot, and excessive VCCA noise, at increasingly severe levels.

Additionally, heavy ion SEE testing will be conducted.

 

Programming Algorithms: Outlook

The new programming algorithm has passed internal qualification at Actel and is utilized in the updated software revision, scheduled for imminent release. Users retain the option of using the old algorithm by not updating their software.

Programming algorithm testing is an ongoing activity at a number of organizations.   Presently available data from the A54SX72A device testing indicates a significant improvement in robustness of programmed antifuses has been achieved by utilizing the new algorithm.  An examination of antifuse stress levels, as tabulated in the Appendix, suggests that the RTSX-S series devices programmed with the new algorithm will also exhibit increased robustness -- consistent with preliminary RT54SX32S testing, where no failures have been detected to date.

It is recommended that, if at all possible, users postpone programming of flight devices at this time and utilize either commercial or other non-flight FPGAs as an interim step, thus permitting flight card development, test, and verification to proceed.  It is strongly advised that users follow test developments closely.

 

Software Version Information

The new programming algorithm for SX-A and RTSX-S series FPGAs, built in the 0.25 µm MEC/Tonami process, will be incorporated in software versions starting with 4.44.0 (Windows) and 3.81 (DOS).

 

References

  1. "NASA Advisory: Actel RTSX-S and SX-A Programmed Antifuses," March 26, 2004.
  2. "OLD News #15: Actel SX-A and RTSX-S Programmed Antifuses," March 17, 2004.
  3. "New Programming Algorithm" Reference 19 for OLD News #15: "Actel SX-A and RTSX-S Programmed Antifuses," April 7, 2004.
  4. "The First Summary Report on the Independent Review of RTSX-S FPGA Reliability on NASA Space Flight Missions," February 11, 2004.
  5. "OLD News #14: Testing and Application of Modern Microelectronic Devices: Do's, Don'ts, and Failures," November 19, 2003.
  6. "3rd Advisory Letter," Actel Corporation, Esmat Z. Hamdy, April 14, 2004.
  7. "2nd Advisory Letter," Actel Corporation, Esmat Z. Hamdy, March 3, 2004.
  8. "Regarding Actel RT54SX32S and RT54SX72S FPGAs," Esmat Z. Hamdy, Actel Corporation, December 16, 2003.
  9. "Actel RTSX-S EOS Information Pack," Actel Corporation, December 2003.
  10. "Handling of Parts - Subsequent Testing or Analysis," March 2004.
  11. "Post Programming Burn In (PPBI) for RT54SXS Actel FPGAs," Dan Elftmann and Minal Sawant, Actel Corporation, 2002 MAPLD International Conference, Laurel, MD., September 2002.
  12. "Reliability of Antifuse-Based Field Programmable Gate Arrays for Military and Aerospace Applications," (figures) McCollum, John, Roy Lambertson, Jeewicka Ranweera, Jennifer Moriarta, Jih-Jong Wang, and Frank Hawley, Actel Corporation, 2001 MAPLD International Conference, Laurel, MD., September 2001.
  13. "Actel 54SX32A Ground Bounce Testing Results," Johns Hopkins University/Applied Physics Laboratory, December 2002.
  14. "Failure Analysis Report for RT54SX72S-CQ256B Group C – RTSX-S Qualification," Solomon Wolday, July 24th , 2002.
  15. "Failure Analysis Report for A54SX72A-CQ208B Group C – HIREL A54SX-A Qualification," Solomon Wolday, July 16, 2003.
  16. "Designing For Signal and Power Integrity in FPGA Systems," Mark Alexander, 2002 MAPLD International Conference, Laurel, MD, September 2002.
  17. "IBIS Models: Background and Usage," Actel Corporation, January, 2002. 
  18. " FPGA High Speed and Signal Quality."
  19. "Drive Strength of Actel FPGAs," R. Katz, NASA Office of Logic Design, March 2004.
  20. "Analysis of Printed Circuit Board Artwork: Bypassing," Rod Barto, NASA Office of Logic Design, March 2004.
  21. "Actel Reliability Report, Q3 2003."

 

Appendix: Antifuse Stress

One measure of antifuse stress, for this class of device, is the ratio of the peak operating current through the antifuse to the programming current through the antifuse.  While absolute values are the manufacturer's proprietary information, the chart below contains normalized values.  It is seen that the highest stress device is the A54SX72A and the lowest stress device is the RT54SX72S.  In general, the RTSX-S series devices, which incorporate series resistors at the output of each R-Cell and C-Cell, have lower stress levels than their commercial/military SX-A counterparts.  This data is for devices built in the 0.25 µm MEC/Tonami process.

Table 1
Normalized IOPERATING/IPROGRAMMING
0.25 µm MEC/Tonami process

  '32 '72
SX-A 0.94 1.00
RTSX-S 0.82 0.79

 

In my new OLD (Office of Logic Design) position, I am now making some of my informal e-mail lists semi-formal. These mailings will have pointers to technical tips that can [hopefully] proactively prevent errors from getting into flight designs or make things go faster and smoother. I have included an array of people from a number of organizations; different NASA Centers, ESA, etc., as you all may distribute to people in your own organizations and other colleagues. Please let me know if you are on this list in error or if someone should be added to it. This list is targeted towards those that either will design or review space flight digital electronics. Feel free to suggest topics for discussion and research or to contribute news items.  [Note for this web-based release: to become a recipient on this mailing list, please send e-mail to: richard.b.katz@nasa.gov.]

All application notes are uploaded onto my www site. New additions are noted on the what's new page. I will give these mailings from time to time; too much and they will be filtered and ignored - too little and not enough information flows. So I'll try and hit a good balance.

whats_new.htm

Best regards,

-- rk

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