May 28, 2003
OLD News #11.
ESD and proper device handling practices are nothing new and normally would not warrant an OLD News posting. Indeed, ESD practice and component tolerance have improved so much over the years that ESD damage hasn't been a major source of problems for quite a while, for regular digital integrated circuits and interface components.
However, there have been some recent surprises. This case study is for an LVDS (low voltage differential signaling) receiver, which is similar to the widely used and familiar RS-422 standard, but is faster, has lower skew, and consumes less power. This device is designed to be an interface component and was not expected to be an "easy" victim of ESD.
A Mercury-bound flight unit was built and went through a full board-level qualification without any problems. Subsequently it was integrated into the flight instrument, seemingly without any problems. Soon afterwards, during the second round of instrument-level "safe-to-mate" testing, atypical behavior was observed on one of the differential inputs of the unit. Troubleshooting indicated a failure in the LVDS receiver. ESD was suspected as the unit was recently handled and manufacturer's data showed that the component has an ESD tolerance of only 250 V (not mentioned in the data sheet). Note that although damaged, the device was still functional.
Since the root cause of this failure was at this time unknown and all LVDS receivers on the board were treated in a similar fashion, all of them were removed and replaced. Unfortunately I&T personnel again performed the "safe-to-mate" test. The unit passed the first "safe-to-mate" test. After some reconfiguration of the instrument it failed the second "safe-to-mate" test, this time in two locations. Since the board was never powered on, electrical overstress could be ruled out and ESD was again suspected. An ESD survey indicated a potential in excess of 500 V on the break-out-box used for the "safe-to-mate" test.
The board was again reworked, all components were replaced, and "safe-to-mate" tests were banned. The devices were sent to the manufacturer, the failures were verified, and analysis indicated damage consistent with ESD events. Photographs, ESD test results, and the report are included below.
Several findings from this case study and other recent examples are:
- Some modern high-speed devices have far lower ESD ratings then expected.
- Devices designed for interface applications can be highly ESD sensitive.
- While safe-to-mate tests may be valuable, unsafe test equipment and improper I&T practices can and does damage flight electronics.
Supplementary Material
Figure 1. Red circle shows the location of the hot spot in all three leaky buffers.
The damage to the devices is consistent with an ESD event.
Table 1. ESD Test Results for UTMC LVDS
Device Type Reports 5V Without Cold Sparing jr05_esd.doc
jr05_esd.pdfjr06_esd.pdf
jr06_esd.doc5V with Cold Sparing jr10_esd.pdf
jr10_esd.docjr11_esd.pdf
jr11_esd.doc3.3V parts wd07.pdf
wd07.docwd08.pdf
wd08.docThe UTMC failure report for this incident is available at: lvds_fa_mla.doc, lvds_fa_mla.pdf
In my new OLD (Office of Logic Design) position, I am now making some of my informal e-mail lists semi-formal. These mailings will have pointers to technical tips that can [hopefully] proactively prevent errors from getting into flight designs or make things go faster and smoother. I have included an array of people from a number of number of organizations; different NASA Centers, ESA, etc., as you all may distribute to people in your own organizations and other colleagues. Please let me know if you are on this list in error or if someone should be added to it. This list is targeted towards those that either will design or review space flight digital electronics. Feel free to suggest topics for discussion and research or to contribute news items. [Note for this web-based release: to become a recipient on this mailing list, please send e-mail to: richard.b.katz@nasa.gov.]
All application notes are uploaded onto my www site. New additions are noted on the what's new page. I will give these mailings from time to time; too much and they will be filtered and ignored - too little and not enough information flows. So I'll try and hit a good balance.
Best regards,
-- rk
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