NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Xilinx Radiation Data

Xilinx Virtex-II Pro PowerPC Proton Test Results David Petrick and Dr. James Howard	Introduction This proton test was performed on multiple XQ2VP40 devices, a dual processor version of the Virtex-II Pro with an epitaxial layer. The XQ2VP40 device was tested using the XRTC board specifically designed for radiation testing of the Virtex-II Pro. Testing was conducted at the Indiana University Cyclotron Facility (IUCF). This report outlines the test setup, design applications, static results for the registers and cache, and various results from executing a dynamic application on the PowerPC.
Neutron-Induced Soft Error Sensitivity Characterization of FPGAs Spartan-3 and Virtex-II/Virtex-II Pro Joe Fabula, Austin Lesea, and Jason Moore R 2004 MAPLD International Conference Presentation: l139_fabula_s.ppt wp216_final.pdf wp216_final_Jason.pdf	Introduction Since 2001, samples of Spartan-3 (90 nm), Virtex-II Pro (130 nm), Virtex-II (150 nm) FPGAs have been tested for sensitivity to neutron-induced upset. Atmospheric neutrons are the residue of cosmic ray showers that originate in deep space and interact with the upper atmosphere. As the atmosphere increases in density at lower elevations, most cosmic rays are absorbed. However, there remains a spectrum of energetic neutrons present at all altitudes due to the nuclear reactions between these cosmic rays and the oxygen and nitrogen atoms in the air. While these neutrons have not been shown to be unsafe for humans, they do interact with matter as governed by the laws of physics. In silicon, the neutrons generate charge through elastic and inelastic collisions and the resultant scattering of atoms. This charge can interfere with the operation of semiconductor devices. As semiconductor technology advances, the amount of charge that is stored in specific nodes in the circuitry continues to decline. The point has been reached where the charge generated by terrestrial neutron interactions with the silicon lattice can cause soft errors known as Neutron-induced Single-Event Upset (NSEU). In a static-latch based FPGA, these upsets can potentially interfere with device operation.
Out of Compliance Solder and Upsets in XC2V FPGAs	Product Advisory Xilinx recently released an advisory about some FPGAs in flip-chip packages were manufactured using solder that may cause upset of configuration memory bits. It was determined that out of compliance "low-alpha" solder was used.
Customer Advisory: Flip-Chip Package Substrate Solder Issue advisory2003-10.pdf^XL	Introduction The purpose of this advisory is to communicate that some Xilinx FPGAs in flip-chip packaging were manufactured using solder material that might cause random upset of device configuration bits.
Flip-Chip Package Substrate Solder Issue wp208.pdf^XL	Introduction Alpha particle emission in close proximity to the device circuitry is minimized by following Xilinx low alpha solder requirements on package substrate pads. One flip-chip packaging vendor’s failure to comply with these requirements has resulted in contamination by high alpha solder causing possible soft errors due to flipped device configuration bits. This white paper provides an overview on soldering material, describes the specific soldering problem, and offers some solutions.
Results and Status of Radiation Testing the Xilinx XQVR300E FPGA Contact for data access test.pdf test.ppt	Prompt Pulse Testing Goals Test Articles Test Setup Dosimetry
Single-Event Upsets in SRAM FPGAs Michael Caffrey¹, Paul Graham¹, Eric Johnson¹, and Michael Wirthlin² ¹ Los Alamos National Laboratory ² BYU Presented at the 2002 MAPLD International Conference, Laurel, MD, September 10-12, 2002. p8_caffrey_s.ppt (presentation) p8_caffrey_p.pdf (paper)	Abstract Field Programmable Gate Arrays (FPGAs) are indisputably useful for space missions where system schedule and cost are critical but production quantity is low. SRAM-based FPGAs are uniquely suited for remote missions because of the ability to change function and because they offer substantial signal processing performance. Single Event Upsets (SEUs) are of utmost concern for SRAM FPGAs because the logic functions themselves are sensitive to unintended change. This paper discusses our work with the Xilinx Virtex FPGA and the current understanding of the device's sensitive cross-section. Also discussed are considerations for SEU detection, and methods for reducing SEU sensitivity and increasing SEU observability.
Data From Single Event Upset Susceptibility Testing of the Xilinx Virtex II FPGA C.C. Yui¹, G.M. Swift¹, C. Carmichael² ¹ Jet Propulsion Laboratory, California Institute of Technology² Xilinx Inc. Presented at the 2002 MAPLD International Conference, Laurel, MD, September 10-12, 2002. virtex2_swift_mapld02.htm	Abstract Heavy ion testing of the Xilinx Virtex II was conducted on the configuration, block RAM and user flip flop cells to determine their single event upset susceptibility using LETs of 1.2 to 60 MeVcm²/mg. A software program specifically designed to count errors in the FPGA is used to reveal LET _(1/e) and single-event-functional interrupt failures. (September 15, 2002)
Summary of Transient Current Data for S/N 42, XQVR300, as a Function of Total Dose transient_esa_2002.htm	Curves showing startup transient current data. (May 20, 2002)
Single Event Upset Simulation for Field Programmable Gate Arrays M. Wirthlin, E. Johnson, Brigham Young University; M. Caffrey, Los Alamos National Laboratory Presented at the 2002 IEEE NSREC Phoenix, AZ	Abstract: FPGAs provide advantages for space-based remote sensing. However, FPGAs are susceptible to singe-event upsets. We describe a single-event upset simulator used to simulate the effects of SEUs within the F GA configuration memory.
esa_qca0109ts_c.pdf	Radiation Pre-Evaluation of Xilinx FPGA XQVR300 CONCLUSION Total Dose: Severe problems to initialise the devices were observed after 45 krad(Si) accumulated total dose. To overcome the problem, a slow power-up ramp was required with the possibility to deliver more current than specified (2-Ampere). The results are in conflict with earlier total dose tests [2,4] that indicate total dose tolerance to about 100 krad(Si). However, no power cycling have been performed in earlier tests. Parameter drift measurements indicated failures at about 80 krad(Si). SEU: The SRAM based cells are sensitive for SEUs down to low LET values. With a Tripple Module Redundant Design in combination with fast correction of configuration data, the majority of all observed errors could be corrected. Errors in the control registers of the device cannot be corrected. (April 17, 2002)
esa_qca0112t_c.pdf	Radiation Evaluation of Power-up Behaviour of Xilinx FPGA XQVR300 CONCLUSION Parameter drift, supply leakage current and time delay measurements indicate small drifts after irradiation. The critical parameter is the current peak at power-up. After 45 krad(Si) accumulated total dose severe problems to initialise the devices were indicated. It was observed that the current peak in the power-up phase strongly increased in width and amplitude with cumulated total dose.The results are well in line with what was observed in the earlier performed total dose test [1]. The two tested power-up ramps indicate that a higher total dose tolerance could be achieved with a slower power-up ramp. Xilinx allow up to 50 ms power-up ramp. The present results are in conflict with earlier total dose tests performed by Xilinx [2,4] where total dose tolerance to about 100 krad(Si) have been reported. These tests have, however, been performed on blank devices with no power cycling during irradiations. (April 17, 2002)
Xilinx_NSREC98.PDF Synopsis	Neutron Single Event Upsets In SRAM-Based FPGAs (.pdf 35kbytes) Abstract SRAM-based FPGAs have been studied for their sensitivity to atmospheric high energy neutrons. FPGAs with the supply voltage 5V and 3.3V were irradiated by 0-11, 14 and 100 MeV neutrons and showed a very low SEU susceptibility.
gingrich1.pdf	Total Ionizing Dose Effects in a SRAM-Based FPGA Abstract We have measured the effects of total ionizing dose on Xilinx XC4036X FPGAs. The FPGAs were irradiated at a dose rate of about 0.5 krad/hr. An average total dose of 39 krad(Si) and 16 krad(Si) were absorved by the XL-series and XLA-series FPGAs, respectively, before the power supply current increased.
gingrich2.pdf	Irradiation of a FPGA in a Submircon CMOS Process Abstract We have measured the effects of total ionizing dose on a XC4036XL-1HQ240C. The FPGA operated without error for 115 days while being irradiated with a dose rate of 87 rad(Si)/hr. A total dose of (236 +/-11) krad(Si) was absorbed before the first error occurred.
SEE_Test_XR4036XL.pdf	Test report on the upset and latchup sensitivity of the XQR4036XL. No latchup up to LET=100 MeV-cm2/mg. Predicted upset rates are shown. (.pdf 54 kbytes).
Xilinx_NSREC2000.pdf	Radiation Characterization, and SEU Mitigation, of the Virtex FPGA for Space-Based Reconfigurable Computing Abstract Orbital remote sensing instruments and systems benefit from high performance, adaptable computing systems. Field programmable SRAM-based gate arrays (FPGAs) are usually the chosen platform for real-time reconfigurable computing. This technology is driven by the commercial sector, so devices intended for the space environment must be adapted from commercial product. Total ionizing dose, heavy ion and proton characterization have been performed on Virtex FPGAs fabricated on epitaxial silicon to evaluate the on-orbit radiation performance expected for this technology. The dominant risk is Single Event Upset (SEU), so upset detection and mitigation schemes have also been tested to validate the improvement in the device upset sensitivity and the system consequence of upsets. (10/28/2000)
XQR4036XL_SEU.pdf	Heavy Ion Cross-section vs. LET curves for the XQR4036XL. (.pdf 8 kbytes).

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