NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Signal Integrity: IBM Luna C DRAM

LUNA-C DD3 16M (4Mx4) DRAM with On-Chip ECC

Signal integrity is important for all devices, of course and it is noted that signal integrity requirements are usually treated as an aside, even by the manufacturers, as well as the user.  However, many DRAM and SDRAM manufacturers make signal integrity requirements very prominent and explicit -- this is not done to make their parts harder to use!  IBM has carefully specified requirements for their 16 Mbit DRAM and the key figures and text is presented below as one specific example.  As always, consult specific data sheets and application notes for each particular design.

Signal Undershoot/Overshoot Requirements

Signal Undershoot/Overshoot Requirements

Allowable Undershoot and Overshoot.  Undershoot/Overshoot shown below Most Negative Down Level (VIL(min)) and above Most Positive Up Level (VIH(max)).

Allowable Input Signal Noise

Allowable Input Signal Noise

Allowable Noise. Noise allowed above Most Positive Down Level (VIL(max)) and below Least Positive Up Level (VIH(min)).

 

Rising and falling edges of control signals (RE, CE, and W) must be monotonic within the VIL(max)-VIH(min) input level band. This prevents accidental triggering of internal timing chains. Failure to follow this rule may produce unpredictable results. The noise allowed in the above curve assumes that the signal goes from VIH(min) down, and returns to VIH(min) or goes from VIL(max) up, and returns to VIL(max) within the pulse width shown.

Power Supply Voltage, Tolerance, and Noise

This module is designed to operate at 3.6 :to.18V.

The DC variation in the VCC supply between each refresh interval (i.e. within 32 ms @ Tj =85ºC) is limited to 250mV. This includes DC plus low frequency (< 60Hz) variations. High frequency noise allowed is shown in Figure 10, and may be superimposed on top of this.

To further illustrate, VCC is permitted between VCC(max) of 3.78V and VCC(min) of 3.42V. Any AC ripple (low freq.uency) is allowed provided that the VCC value does not change by more than 250mV per tREF interval. In addition to this low frequency noise, spikes are allowed on top of the ripple consistent with the diagram below. .

POWER SUPPLY NOISE TOLERANCE CURVE

Figure 10.  LUNA 4Mx4 Power Supply Noise Tolerance Curve (Power Supply Variation (mV) vs. Time (ns)).

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