NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

 

SEU Hardening of Flip-Flops

Title, Authors, Reference, Link Abstract, Summary, Conclusions


TD1822 0.25 mm SEE Test

BNL0199
January 25, 1999

td1822_bnl0199.pdf

 Overview

SEE Test of Prototype 54SX-A devices.  Both R-Cell and C-C flip-flops were tested.  No antifuse rupture or latchup detected.


Functional Triple Modular Redundancy (FTMR): VHDL Design Methodology for Redundancy in Combinatorial and Sequential Logic

Design and Assessment Report

FPGA-003-01, Version 0.2
December 2002
Prepared by Sandi Habinc

functional_tmr_fpga_003_01-0-2.pdf

 Scope

This document discusses the use of Triple Modular Redundancy (TMR) for the protection of combinatorial and sequential logic in reprogrammable logic devices. A VHDL approach has been developed for automatic TMR insertion and a demonstration design has been developed.  The approach is called “Functional Triple Modular Redundancy (FTMR)”.

This document addresses the protection of random sequential and combinatorial logic. This document does not address the protection of inputs and outputs, the usage of on-chip block memories or dedicated shift-registers etc. It assumes a good knowledge of the Xilinx architecture. For detailed information on Xilinx FPGAs and mitigation techniques such as configuration memory scrubbing, see [RD7].


Single Event Upset (SEU) Mitigation by Virtual Triple Modular Redundancy (TMR) in Design Reduces Manufacturing Cost and Lowers Power

Alternative System Concepts, Inc., supported by: BMDO, JHU/APL, NIST Manufacturing Extension Program, and ASC

virtual_tmr_asc.pdf
virtual_tmr_asc.doc

 Abstract
In this white paper we describe a Concurrent Error Detection (CED) technique that uses idle cycles in a data path to do the re-computation in what is called "Virtual Triple Modular Redundancy (TMR)." This new design technique uses a special synthesis tool to automatically generate architectures for mitigating SEU using commercial grade FPGAs or ASICs. Total dose and other long-term effects of radiation are not considered. The development by Alternative System Concepts, Inc. (ASC) and Polytechnic University of the Virtual TMR Tool was partially funded by SBIR Phase I and Phase II BMDO contacts managed by Army SMDC. We will demonstrate its benefits and drawbacks using RC6 encryption as a case study. The idle cycle based CED has low area overhead and performance penalty while maintaining strong CED capability. An extra inherent benefit of the technique is increased manufacturing yield.


SEU Hardening Techniques for Retargetable, Scalable, Sub-Micron Digital Circuits and Libraries

M. P. Baze, J. C. Killens, R. A. Paup, W. P. Snapp
Boeing Space and Communications, Seattle, WA

Thirteenth Biennial Single Effects Symposium
Manhattan Beach, CA, April, 2002

baze_see_mit_seesymp02.pdf
baze_see_mit_seesymp02.ppt

 Summary
  • A number of design options exist for improving the SEU hardness of digital logic.
  • However, specific considerations and restrictions must be observed for each technique if these techniques are to be applied over a range of process technologies and reduced feature size.

Includes a nice table comparing different flip-flop hardening techniques vs. power, area, speed, and hardness.

(May 7, 2002)


An Error Correction Code to Address Neutron Single Event Upsets in Semiconductor Memory

David W. Jensen, Ph.D.
Advanced Computing Systems
Rockwell Collins

Thirteenth Biennial Single Effects Symposium
Manhattan Beach, CA, April, 2002
jensen_rockwell_seesymp02.ppt


Introduction and Summary

  • Why concerned about Neutron Single Event Upsets (NSEUs)?
  • Error correction codes
  • Combining multiple mitigation techniques could enable an NSEU-tolerant, commercially-fabricated microprocessor

  • Presented efficient error correction block code to address Singe Event Upsets (SEUs) and Multiple Bit Upsets (MBUs) in semiconductor memory

Note: Could not make a .pdf file.  (May 3, 2002)
72A_vs_72S.jpg Comparison of 0.25 um MEC die: A54SX72A vs. SEU-hardened RT54SX72S.
32A vs. 32S  
MRC_SEU.pdf Temporally Redundant Latch for Preventing Single Event Disruptions in Sequential Integrated Circuits
Abstract -
IC designs have experienced dramatic increases in both density and speed. These advances are not without serious implications for microelectronics used in space applications where ICs are subjected to hostile environments that include single event effects (SEE) primarily do to interactions with cosmic rays, high energy protons, and high energy neutrons.

This report will:

1. provide some background to the reader in the area of SEU mechanisms and
    describe their implications for present day spaceborne microelectronics.
2. clarify the impact that shrinking device sizes will have on single event upsets
    in spaceborne microelectronics
3. explain how single event transients (SETs) in the combinatorial logic of a circuit
    will become important in spaceborne systems, and
4. propose a new and unique circuit design methodology that can, with minor tradeoffs,
    totally eliminate SEUs and even multiple bit upsets (MBUs) from sequential circuit designs.
appnote1.pdf "Design Techniques For Radiation-Hardened Field Programmable Gate Arrays," R. Katz and K. Hayes.  A summary on the radiation performance of the RH1280 and design techniques for the device.  Adapted from our 1994 NSREC/IEEE TNS paper. (.pdf 74 kbytes)
email rich "Hardening Flip-Flops for Actel FPGAs for schematic, macro, and HDL Design,"
Abstract
Recently we've designed a library with C-Module substitutes for all S-Module flip-flops and latches with hooks are in for TMR.  These libraries can be used in several ways. One, they can be used as a standard macro library and one can pick from the list. This is handy for schematic-based design and permits use of 'standard' macro definitions. For Actgen or VHDL-based designs, we have written a utility to automagically make substitute C-Module replacements for all S-Module flip-flops and latches. This can be done globally or on a case by case basis. This program and the macro library is for Viewlogic systems and it automates what one can do by hand. It should easily be ported to Orcad or other systems.   Note that Viewgen will create a valid schematic file from Actgen or VHD generated netlists, permitting use of standard tools such as Actmap and post-processing the netlists.
SynplicitySEUControl.htm "Using Synplicity to Control Flip-Flip Implementation for SEU-Hardness"
Abstract
A procedure is given and discussed on now to use Synplicity to control the flip-flop implementation.  Either C-Mod flip-flops or TMR implementations are generated from VHDL or Verilog HDL code.
synopsis_actel.pdf "Using Synopsis to Design Actel's Radiation-Hardened FPGAs,"
Abstract
This application note shows how to use Synopsis automation scripts to control synthesis such that SEU soft flip-flops (S-Module flip-flops) are excluded from the synthesized output.  The synthesis can be controlled to either use radiation-tolerant flip-flops (C-Module or C-C flip-flops) or triple-modular redundant (TMR) structures. (.pdf 39 kbytes)
Act1_SEU_Hardening.pdf K-Mod Flip-Flop SEU test results.  The K-Mod flip-flop uses 4 C-Modules in a mirror topology.  This results in an increase in the SEU LET threshold as well as a substantial decrease in the upset cross-section. (.pdf 12 kbytes).
SX_SEU_Hardening_BNL1198.pdf
SX-CC_Flip-Flop.jpg		 SX "C-Mod" Flip-Flop SEU test results.  "C-Mod flip-flops were constructed in a prototype RH54SX16 - note that these flip-flops are not a part of the SX architecture.  This results in an increase in the SEU LET threshold as well as a substantial decrease in the upset cross-section. (.pdf 15 kbytes)
Schematic of flip-flop added December 7, 2000.
SEU_Hardening_C2468_BNL0199.pdf More "K-Mod" Flip-Flop SEU test results using an A1280A.  This version uses 4 strings of flip-flops, ranging from 1 to 4 mutiplexors per latch.   This results in an increase in the SEU LET threshold as well as a substantial decrease in the upset cross-section.
SEU Hardening Patents and References.htm SEU Hardening Patents and References.  Lists patent numbers, dates, and a brief description.
Test_BNL0800.htm First test of K-Latch @ BNL, August, 2000.  Preliminary/Experimental Concept Run.
Test_BNL0900.htm Second test of K-Latch @ BNL, September, 2000.  Preliminary/Experimental Concept Run.
Test_BNL1000.htm Third test of K-Latch @ BNL, October, 2000.  DUT uses HCLK w/ JTAG properly configured.  Preliminary/Experimental Concept Run.  (Oct. 27, 2000).
BNL_08_01_SX72S_MEC.htm First test of the RT54SX72S (K-Latch) at BNL, August, 2001.  S/N LAN6201, LAN6202.

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