NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

FPGA Reliability

Destructive Physical Analysis: RT54SX and RT54SXS

Destructive Physical Analysis: Xilinx

Destructive Physical Analysis: RTAX-S

Destructive Physical Analysis: Aeroflex Eclipse

Title, Authors, Reference	Abstract/Conclusion
“RT54SX-S, RTSX-SU, RTAX-S, and Eclipse FPGAs for Spaceborne Application Briefing” This Briefing was held at the NASA Goddard Space Flight Center on May 10, 2006.	This briefing consisted of a set of talks from inside and outside NASA, with an emphasis on device reliability.
“RT54SX-S, RTSX-SU, RTAX-S, and Eclipse FPGAs for Spaceborne Application Briefing” This Briefing was held at the NASA Goddard Space Flight Center on January 18, 2006.	This briefing consisted of a set of talks from inside and outside NASA, with an emphasis on device reliability.
"ESD Sensitivity of Actel RTSX-SU Field Programmable Gate Arrays"	Summary ESD data for the RTAX-S FPGA for machine, human body, and charged device models. Data presented at the “RT54SX-S, RTSX-SU, RTAX-S, and Eclipse FPGAs for Spaceborne Application Briefing” held at the NASA Goddard Space Flight Center on May 10, 2006.
Destructive Physical Analyses (DPAs) on Field Programmable Gate Arrays (FPGAs) and Non- Volatile Memory Devices, Failure Reports, and Lessons Learned NASA Advisory NA-GSFC-2006-01 January 12, 2006	Summary In both FPGA and EEPROM device applications, the realization of past parts issues was delayed, since the failure rate was low. Failures in non-flight parts are not always treated with the same rigor as failures in flight qualified devices. Additionally, proprietary and stove-piped information barriers, along with a cultural resistance to discussing failures, prevent the user community from pooling their data collectively, observing trends, and “connecting the dots.” Together, this had led to delays in manufacturers improving their parts, processes, and software. NASA GSFC kindly requests other NASA and non-NASA programs and projects to share with the Advisory Technical Point of Contact (see block 13) all DPA and Failure Reports on FPGAs and non-volatile memory devices, from both flight and engineering model usage along with lessons learned that can benefit the community. Note that prior to dissemination on the NASA Office of Logic Design web site, appropriate care (i.e. deleting items such as contractor names) will be taken.
AX and RTAX-S FPGA Bond Wires	Summary In previous generation Actel FPGAs such as the RT54SX, the RT54SX-S, and the RTSX-SU, gold ball bonds were used on aluminum pads. A concern is the formation of intermetallic compounds. Early generation Actel devices utilized aluminum wires. AX FPGAs, used for commercial, industrial, and military applications, employ gold bond wires. The RTAX-S, designed for space applications, has been designed for aluminum bond wires. Sample images are posted.
DPA: AT40KEL040KW1-E June 21, 2005	DPA Number: 55334 Manufacturer: Atmel Lot/Date Code: 0433
NASA Advisory: Actel SX-A, RTSX-S, and RTSX-SU FPGAs in Mission and Safety-Critical Systems. November 29, 2004 NA-GSFC-2005-01	Actions Recommended: Actel MEC SX-A FPGAs should not be used in safety-critical applications. Actel MEC RTSX-S FPGAs should not be used in manned, safety-critical applications. These two recommendations apply to both the “old” and “new” programming algorithms. Some faults present in the flight hardware may be undetectable. Other premature failures may manifest themselves after the conclusion of the test program. Current and prospective users of Actel UMC A54SX-A and the new Actel UMC RTSX-SU FPGAs are urged to follow the NASA Office of Logic Design UMC device testing progress (See www.klabs.org for latest results). Actel internal testing has detected no programmed antifuse failures on these two UMC device types. It is recommended that projects employ the following three techniques to decrease the risks associated with the usage of Actel MEC SX-A and Actel MEC RTSX-S FPGAs (Note: also recommended for Actel UMC FPGAs): Ensure that test procedures have maximized fault coverage and all circuit nodes are heavily exercised. Maximize the number of operating pre-launch hours, in particular high temperature environmental testing. Ensure that all specifications, manufacturer’s guidance and good engineering practices are always followed with conservative design practices employed. In particular, logic structures that use the routed array clocks or local signals must employ skew-tolerant clocking techniques.
A54SX-A/UMC and RTSX-SU Comparison Notes	Introduction The A54SX-A and RTSX-SU series devices are quite similar in many ways. However, there are significant differences in a number of aspects. Those differences will be the subject of this application note. This application note applies to UMC produced devices only. The A54SX-A series of devices are used for commercial, industrial and automotive, and military high-reliability applications, as well as for usage in spaceflight prototypes. The RTSX-SU series of devices is designed specifically for spaceflight usage or in other radiation environments.
ESD Sensitivity of Actel RTSX-SU Field Programmable Gate Arrays March 10, 2005	Problem Description Actel performed ESD tests on 6 Field Programmable Gate Arrays (FPGAs) with p/n RTSX32SU-CQ256 using the HBM (Human Body Model) per MIL-STD-883F (Method 3015.7). The 3 FPGAs that were tested at 75 volt zap voltages all passed. Three other FPGAs had ESD test failures that were documented at the following zap voltages: 100V, 150V, and 200V.
OLD News #17: Actel SXA, RTSX-S, and RTSX-SU FPGAs in Mission- and Safety-Critical Systems November 2, 2004.	Problem Description RTSX-S and SX-A FPGAs produced in the 0.25 µm MEC/Tonami process have experienced programmed antifuse parametric failures during controlled laboratory testing, with the number of failures significantly exceeding the expected fall out rate for a part of this class. These failures were detected in devices operated in an in-specification electrical environment, utilizing the “old" programming algorithm. Failures were also detected in devices programmed with the "new" programming algorithm at the "4B2" stress level. Data sets show a decreased failure rate for devices programmed with the new programming algorithm at varying levels; some of the most recent failures are still undergoing analysis and may be the result of lot-specific or wafer-specific processing problems or variations. As a result, Actel has implemented a new wafer level visual inspection; 4 die from each wafer will be examined for alignment and photoresist residue. A significant number of failures of this class may not detectable by testing either at the part level by ATE or at the board or box level in the target system. The failure mechanism is a timing fault, and requires that testing be sensitive to timing faults. An examination of the current test data shows a failure rate decreasing with time and accelerated by a combination of increased voltage and temperature. Detailed information can be provided upon request. No programmed antifuse failures have been observed to date in the 0.22 µm SX-A, 0.22 µm eX, or 0.25 µm RTSX-SU FPGAs produced at the UMC foundry. These UMC-produced devices have an antifuse structure physically different from those produced in the MEC foundry. Additionally, there were other design changes at the circuit and structural levels.
NASA Advisory: Testing of Actel SX-A and RTSX-S Programming Algorithms June 22, 2004 NA-GSFC-2004-08	Recommendations Actel has released and recommends use of a new programming algorithm for the SX-A and RTSX-S devices built in the 0.25 micron MEC/Tonami process. Users must note that the qualification program was conducted at high temperatures only and that comprehensive temperature data is not yet available. NASA will produce a comprehensive data set, including both cold (-55 degrees C.) and hot (+125 degrees C.) temperatures, under the sponsorship of the NASA Engineering and Safety Center (NESC). Test devices will consist of 300 RTSX-S 0.25 µm MEC devices and 300 RTSX-SU 0.25 µm UMC devices. For further information, contact Rich Katz or your resident FPGA expert. Users retain the option of using the old programming algorithm by not upgrading their software and must note that there are a significant number of programmed antifuse failures that are under investigation (Reference: NASA Advisory NA-GSFC-2004-06). All relevant personnel must also review NASA Advisory NA-GSFC-2004-06, and the documents referenced, to ensure that all specifications, manufacturer’s guidance, and good engineering practices are always followed and conservative design practices employed.
3^rd Advisory Letter Esmat Z. Hamdy Actel Corporation April 14, 2004 Data on the New Programming Algorithm	Excerpt As you know, Actel is conducting ongoing investigations regarding a limited number of observed field failures of our RT54SX32S and RT54SX72S FPGAs. To date, all of the devices that we have analyzed with confirmed damage were found to have been subjected to electrical overstress conditions.A large amount of the experimentation and analysis conducted during the course of this investigation has been directed at quantifying the effects on our devices when used outside the datasheet limits. In addition, we have evaluated various programming algorithms. The purpose of this evaluation is to determine if anything can be done at the programming stage to increase the capability of our RT54SX32S and RT54SX72S devices to operate in out-of-specification conditions. A revised programming algorithm currently under evaluation has been shown to provide enhanced resistance to electrical overstress. Subject to further qualification testing, our intention is to ship this new programming algorithm in mid-May.
NASA Advisory: Actel RTSX-S and SX-A Programmed Antifuses. NA-GSFC-2004-06 March 26, 2004 na-gsfc-2004-06.pdf	Actions Recommended: All relevant personnel should ensure that all specifications, manufacturer’s guidance, and good engineering practices are always followed and conservative design practices should be employed; failure to follow such an approach appears to correlate with device failure.
2^nd Advisory Letter Esmat Z. Hamdy Actel Corporation March 3, 2004	Introduction Actel is conducting ongoing investigations regarding a limited number of observed field failures of our RT54SX32S and RT54SX72S FPGAs. To date, all of the devices that we have analyzed with confirmed damage to the antifuse elements were found to have been subjected to electrical overstress (EOS). We continue to believe that our devices are reliable when used within the datasheet limits. Some of our customers believe that the cause of these failures has not yet been properly identified. Because of this, our detailed investigation to identify the root cause is continuing. We are aware that reliability is a major factor in the selection of devices for space flight applications and are committed to resolving these open issues. Several of our Space customers have been very actively involved in the ongoing investigations, and we appreciate their assistance.
The First Summary Report on the Independent Review of SX-S FPGA Reliability on NASA Space Flight Missions February 11, 2004 fpga_iat_summary1_final.doc	Overview Enclosed is the first summary report on the SX-S FPGA reliability for NASA space flight missions. This report provides a snapshot of the work accomplished to date, including the meeting held at NASA GSFC on January 7, 2004, a review of all available data and reports, and extensive analysis performed over the past month. A diverse team of 10 engineers from various NASA Centers and the Department of Defense was assembled for this task. The primary objective of this activity is to determine the root cause of failures of Actel SX-S devices, which are used extensively in NASA's spacecraft, both crewed and robotic, as well as to offer guidance to engineers testing and using these devices. This summary documents the findings and recommendations for the use of these devices in NASA and other mission- or safety-critical systems. A NASA Advisory will be submitted for dissemination, applications notes published, and seminars held to maximize the reliability of digital electronics systems.
Actel Advisory Letter and Background Information on the Actel SX-S Antifuse	Contents Advisory Letter Background Information
RH1280 Lifetest Delta Data (raw)	Data for binning delay and standby current.
Failure Analysis Report for A54SX32A-PQ208 Prepared for NASA September 3rd, 2003 sx32a-pq208_nasa_report_rev3.pdf	DEVICE TYPE: A54SX32A-PQ208 DATE CODE: 01/10 WAFER LOT #: T25J008 Design Name: CPU_SIM.adb Shift register on global routed clock failed.
proasic_reliability_april_2002/	ProASIC Reliability Report, April 2002
Product Qualification Report For RT54SXS (72S & 32S) July 2002 qual_report_sxs_july_2002.pdf	Introduction Following qualification report covers the RT54SX-S (32 & 72) product family. This report includes the qualification summary in detail. Additional information like the characterization, data sheets, Total Ionizing Dose (TID) Data reports, bonding diagrams are included here for reference. All units are fabricated at MEC (Matsushita Electronic Corporation). The qualification for this family was done on the largest die available "RT54SX72S ". A QCM design was generated and used to program the devices for Group C testing. For additional details refer Appendix B. Qualification process was completed and product was released for manufacturing on 2-14-2002.
A1020B and A1280A Life Test From "Evaluation of Actel A1020 and A1280A Field Programmable Gate Arrays, Parts Technology Report 64198, February, 1996 life_test_96	TEST PROGRAM Long term reliability was evaluated by subjecting sample devices to 1000-hour static and/or dynamic burn-in at 125°C. All of the devices submitted for life testing were pre-programmed using the test chip pattern described in the radiation testing. Electrical testing was performed initially at 25 °C, according to the test conditions in Table II. Interim and final electrical measurements at 25 °C were made after 500 hours and 1000 hours, respectively. A static life test was performed on twenty two A1280A's (LDC 9411). These parts were provided by the HST Project from their flight lot procurement. Dynamic life tests were performed on six A1020B (LDC 9424). Three of these devices were burned-in at V_CC = 5.5 V and the other three were burned-in at 6.0 V, to determine if the higher burn-in voltage would induce early failures in these devices.
Military Product Qualification of RT54SX72S (rev. 1) and RT54SX32S (rev. 2) with MEC 0.25 µm Technology Report No. M014 rtsx72s_rev1_rtsx32s_rev2_qual_approval.pdf	Conclusion The RT54SX72S qualification devices have passed all requirements specified in the Qualification Proposal. Please refer to the summary table below for individual test results. Therefore, RT54SX72S (rev. 1) and RT54SX32S (rev. 2), are hereby qualified and shall be released for production. Note: This qualification is to qualify the largest RT54SX72S device of the SXA/S family, and re-qualify the RT54SX32S device after mask changes. The RT54SX32S (rev. 2) devices are identical to the RT54SX72S (rev. 1) devices in design and process, but with smaller gate counts, therefore, it is qualified by extension. This qualification effort is a supplement to the commercial SXA family qualification which had previously been performed on A54SX72A and A54SX32A devices with MEC 0.25 µm technology. HTOL, LTOL, and Temp Cycle qualification had all be performed and all requirements have been met. (added June 27, 2002)
Military Process Qualification of RT54SX32S for MEC 0.25 Technology Report No. M010 32s_p03_qual_summary.pdf	Conclusion The 0.25 µm RTSX32S for MEC (wafer lot number T25JSP03) satisfies all requirements specified in the Qualification Proposal. Note: This qualification is a supplement of the commercial qualification, previously performed on A54SX32A and A54SX72A for MEC (0.25 µm technology). HAST, HTOL, LTOL, and Temp Cycle qualifications have been performed and all requirements were met. (added June 27, 2002)
"Study on the increase in ICCI Current for RT54SX32S lot # T25JSP03 and RT54SX72S lot T25KS001 with VCCI = 5V (± 10%) Operation" November 21, 2001 rtsxs_icci_white_paper_final.pdf e-mail for access
Dynamic Burn-In of 1280ARPQG for the Hubble Space Telescope hst_sei.htm	SUMMARY Two parts were submitted to dynamic burn-in using the dynamic bum-in boards supplied by JACKSON and TULL. Device serial # 127 was placed on bun-in board # 00 I and device serial # 128 was placed on bum-in board # 003. Both devices had their RESET pins connected to ground according to JACKSON and TULL's instructions (On each of the bum-in board, J104 and J95 were tied to ground). The bum-in conditions for the first twelve hours were: T_A = 100 °C and V_CC = 5.25V. Subsequently, these conditiom were changed to T_A = 125 °C and V_CC = 5.5 based on telephone conversation between UNISYS and the manufacturer (SEI). The signals were periodically checked at the test point provided on the burn-in boards. The duration of the burn-in was 160 hours. Throughout the burn-in, no significant changes were noted in V_CC, I_CC and the test signals. Pre and post elecffical measurements could not be performed by UNISYS (No ATE program was available for this particular design configuration). (Added June 18, 2002)
Programmable Logic Device Survey http://osat-ext.grc.nasa.gov/rmo/plcsurvey/index.html or contact Kalynnda.Berens@grc.nasa.gov	Abstract If you use programmable logic devices as a NASA Civil Servant of contractor, please take a few minutes to complete a NASA-wide survey. This survey is run from Glenn Research Center, funded by the NASA IV&V Center. It is being used to understand where programmable logic is used throughout NASA, and what assurance activities are performed (June 3, 2002)
	Fit rates over time for new and old Xilinx products. (4/7/2002).
JPL_92-22.htm	Field Programmable Gate Arrays: Evaluation Report for Space-Flight Application JPL Publicatin 92-22, September 15, 1992
Call For Failures: Programmable Device Reliability - NEW!!	While the reliability of programmable logic devices is quite good, they do have a measurable failure rate. A database of device failures is being established. This will enable us to measure field reliability, categorize the failure modes, and spot trends as early as possible.
Odyssey_FPGA_IAT_Report.pdf	Report of the Odyssey FPGA Independent Assessment Team Donald C. Mayer, The Aerospace Corporation Richard B. Katz, NASA/Goddard Space Flight Center Jon V. Osborn, The Aerospace Corporation Jerry M. Soden, Sandia National Laboratories Note that after the report was written, a third failure from the same sublot, on other program, was discovered. Other reports and an alert are in the process of being prepared and released. Contact rich.katz@gsfc.nasa.gov for additional information.
qlogic_reliability_report_q4_2004.pdf qlogic_reliability_report_q1_2003.pdf qlogic_reliability_report_q2_2002.pdf Q_Logic_REL98d.PDF Q_Logic_RELMON98.PDF	Quicklogic Reliability Report, Q4, 2004 Quicklogic Reliability Report, Q1, 2003 Quicklogic Reliability Report, Q2, 2002 Quicklogic Reliability Reports, 1998. Quicklogic Reliability Reports, 1998.
Amkor_Moisture.pdf	MQFP Moisture Absorption / Desorption Data
QYH500_DPA.pdf	DPA of the QYH530 (one mask) ASIC used for COTS-2/STRV-1d. (.pdf 4.3 megabytes)
altera_reliability_q202.pdf	Altera Reliability Report 37, Q2, 2002.
Xilinx_Reliability_0199.pdf Xilinx_Reliability_0499.pdf Xilinx_Reliability_1099.pdf Xilinx_Reliability_0400.pdf Xilinx_Reliability_1001.pdf Xilinx_Reliability_0102.pdf Xilinx_Reliability_0504.pdf Xilinx_Reliability_2004_Q3.pdf Xilinx_Reliability_2004_Q4.pdf Xilinx_Reliability_2005_Q2.pdf	Xilinx Reliability Report, January, 1999. Xilinx Reliability Report, April, 1999. Xilinx Reliability Report, October, 1999. Xilinx Reliability Report, April, 2000. Xilinx Reliability Report, October, 2001 Xilinx Reliability Report, January, 2002 Xilinx Reliability Report, May 2004 Xilinx Reliability Report, January, 2005 Xilinx Reliability Report, March, 2005 Xilinx Reliability Report, August, 2005
Xilinx_QML_ISO.htm Up-Screening of Xilinx Products	Xilinx Awarded Full XML Status. Note by Joseph J. Fabula , Director, Quality Assurance
Actel_Reliability_0299.pdf Actel_Reliability_Q299.pdf Actel_Reliability_Q499.pdf Actel_Reliability_Q100.pdf Actel_Reliability_Q300.pdf Actel_Reliability_Q400.pdf Actel_Reliability_Q301.pdf Actel_Reliability_Q401.pdf Actel_Reliability_Q202.pdf Actel_Reliability_Q302.pdf Actel_Reliability_Q402.pdf Actel_Reliability_Q103.pdf Actel_Reliability_Q203.pdf Actel_Reliability_Q303.pdf Actel_Reliability_Q403.pdf Actel_Reliability_Q104.pdf Actel_Reliability_Q304.pdf Actel_Reliability_Q205.pdf Actel_Qual_RelGuide_Feb01.pdf	Actel Reliability Report, February, 1999. Actel Reliability Report, Q2, 1999. Actel Reliability Report, Q4, 1999. Actel Reliability Report, Q1, 2000. Actel Reliability Report, Q3, 2000. Actel Reliability Report, Q4, 2000. Actel Reliability Report, Q3, 2001. Actel Reliability Report, Q4, 2001. Actel Reliability Report, Q2, 2002. Actel Reliability Report, Q3, 2002. Actel Reliability Report, Q4, 2002. Actel Reliability Report, Q1, 2003. Actel Reliability Report, Q2, 2003. Actel Reliability Report, Q3, 2003. Actel Reliability Report, Q4, 2003. Actel Reliability Report, Q1, 2004. Actel Reliability Report, Q3, 2004. Actel Reliability Report, Q2, 2005. Quality & Reliability Guide, February 2001
Actel_QML.htm Actel_QML_Plastic.htm	Actel Awarded Full QML Status Actel Awarded QML Status (Plastic Packages)
lattice_reliability_2002_1h.pdf	This report summarizes the reliability testing results for Lattice Semiconductor products as of July 2002 and coveres ORCA, ispLSI, ispGDX, ispMACH, GAL Products.
rtsx-su_m-023_qualreport.pdf

Destructive Physical Analysis: Aeroflex Eclipse

Physical Analysis (DPA) Aeroflex Eclipse

May 2006

Summary: Two Aeroflex Eclipse FPGAs were sent to Hi-Rel Laboratories for a destructive physical analysis (DPA). The testing was performed in accordance with MIL-STD-1580B REQ. 16.1, MIL-STD-883 Method 5009, and applicable military standards. Both devices met the specified DPA requirements.

Destructive Physical Analysis: RTAX-S

Destructive Physical Analysis (DPA) - RTAX1000S, D/C 0546 - January, 2006	Summary: Three RTAX1000S FPGAs were sent to Hi-Rel Laboratories for a destructive physical analysis (DPA), focusing on a SEM examination of the bond wire to die interface and pull tests. The testing was performed in accordance with GSFC S-311-M-70, MIL-STD-1580B REQ. 16.1, MIL-STD-883 Method 5009, and applicable military standards. Part Number: RTAX1000S Package: CQ352 Lot Date Code: 0546 Wafer Date Code: ??????
RTAX1000S Destructive Physical Analysis (DPA) - D/C 0444 - December, 2005	Summary: Two RTAX1000S FPGAs were sent to Hi-Rel Laboratories for a destructive physical analysis (DPA). The testing was performed in accordance with GSFC S-311-M-70, MIL-STD-1580B REQ. 16.1, MIL-STD-883 Method 5009, and applicable military standards. Issues were found with the wire bonds on the first device, S/N 61287, and the analysis was stopped. Additional devices have been sent to DPA Laboratories for analysis. Part Number: RTAX1000S Package: CQ352 Lot Date Code: 0444 Wafer Date Code: D1GAH1
RTAX250S Destructive Physical Analysis (DPA) - December, 2005	Summary: Two RTAX250S FPGAs were sent to Hi-Rel Laboratories for a destructive physical analysis (DPA). The testing was performed in accordance with GSFC S-311-M-70, MIL-STD-1580B REQ. 16.1, MIL-STD-883 Method 5009, and applicable military standards. The two devices meet the specified DPA requirements. Part Number: RTAX250S Package: CQ352 Lot Date Code: 0507 Wafer Date Code: D1H381
RTAX2000S Destructive Physical Analysis (DPA) December, 2005	Summary: Two RTAX2000S FPGAs were sent to Hi-Rel Laboratories for a destructive physical analysis (DPA). The testing was performed in accordance with GSFC S-311-M-70, MIL-STD-1580B REQ. 16.1, MIL-STD-883 Method 5009, and applicable military standards. The two devices meet the specified DPA requirements. Part Number: RTAX2000S Package: CQ352 Lot Date Code: 0509 Wafer Date Code: D1KHN1

Destructive Physical Analysis: RT54SX and RT54SXS

RT54SX32SU-1CQ208BX1

Report Number: Q50003DPA
Date Code: 0437
Lot Code: D122H1.
Report Date: 09 Feb 2005

DESTRUCTIVE PHYSICAL ANALYSIS: Destructive Physical Analysis (DPA) was conducted per GSFC S-311-M-70 on one (1) part.

RESULT: The device met the requirements of GSFC S-311-M-70.

RT54SX-S and RTSX-SU Gold Bonding Reliability Evaluation

Raymond Kuang and Randy Sampan
March 4, 2005

Objective
The purpose of this evaluation is to collect additional data for the Au-Al interconnect reliability on RT54SX-S (devices RT54SX32S and 72S), and RTSX-SU (devices RTSX32SU and 72SU) in a hermetically sealed Ceramic QFP.

Summary (excerpt)

RT54SX-S and RTSX-SU devices from different lot date codes were stored in a 150°C environment for 500 hours, 750 hours, and 1,000 hours. Bond pull testing was performed on all wires at three sides of each device, and the result shows bond strengths were above or met the MIL-STD-883 TM 2011 minimum requirement of 2.5 gram-force.