NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

 

Antifuse Notes


Evaluation of SiO2 Antifuse in a 3D-OTP Memory

Feng Li, Xiaoyu Yang, Albert T. Meeks, James T. Shearer, and Kim Yen Le
IEEE Transactions on Device and Materials Reliability
Vol. 4, No. 3, September 2004
pp. 416-421

 Abstract
We have evaluated an antifuse technology used in a novel three-dimensional one-time-programmable (3D-OTP) nonvolatile solid-state memory. The 3D-OTP memory uses deposited polysilicon antifuse sandwiches to build its memory cells. The polysilicon based SiO2 antifuse show different breakdown characteristics compared to conventional traditional gate oxides. Long-term storage tests show that this 3D-OTP solid-state memory not only can be a general purpose ROM, but also can be an ideal media for archiving.

 

SX-SU Rupture Test, BNL, November 2004		 Summary (excerpt)
  • This is an Single Event Effects test of the RT54SX32SU, 0.25 µm, UMC die and A54SX32A, 0.22 µm die for heavy ion exposure.
  • Rupture was observed in multiple samples of both device types.  Note that almost all antifuse devices have been seen to rupture over multiple manufacturers; the single exception is the 0.6 µm RTSX MEC FPGA. Current strip charts are given for all rupture events.
  • Functional failure and intermittent operation was observed; most ruptures did not result in functional failure. 


RT54SX72SU Unprogrammed Antifuse Heavy Ion Test

April, 2004
bnl_04_2004_sx72su.htm

 Summary
This is an Single Event Effects test of the RT54SX72SU, 0.25 µm, UMC die for heavy ion exposure. Only results from the unprogrammed antifuse rupture portion of the test will be reported here. This test was run with both minimal supply voltages for the SEU portion of the tests and maximum voltages for the unprogrammed antifuse portion of the test. All runs will be reported.


3rd Advisory Letter

Esmat Z. Hamdy
Actel Corporation
April 14, 2004

Data on the New Programming Algorithm

 Excerpt
As you know, Actel is conducting ongoing investigations regarding a limited number of observed field failures of our RT54SX32S and RT54SX72S FPGAs. To date, all of the devices that we have analyzed with confirmed damage were found to have been subjected to electrical overstress conditions.A large amount of the experimentation and analysis conducted during the course of this investigation has been directed at quantifying the effects on our devices when used outside the datasheet limits.

In addition, we have evaluated various programming algorithms. The purpose of this evaluation is to determine if anything can be done at the programming stage to increase the capability of our RT54SX32S and RT54SX72S devices to operate in out-of-specification conditions.  A revised programming algorithm currently under evaluation has been shown to provide enhanced resistance to electrical overstress. Subject to further qualification testing, our intention is to ship this new programming algorithm in mid-May.


Sample Antifuses: Programmed and Unprogrammed

Data from:

"Reliability of Antifuse-Based Field Programmable Gate Arrays for Military and Aerospace Applications," (figures)
McCollum, John, Roy Lambertson, Jeewicka Ranweera, Jennifer Moriarta, Jih-Jong Wang, and Frank Hawley
Actel Corporation
2001 MAPLD International Conference, Laurel, MD., September 2001.

 Samples:

Unprogrammed ONO AntifuseProgrammed ONO AntifuseUnprogrammed Metal-to-Metal AntifuseProgrammed Metal-to-Metal Antifuse


2nd Advisory Letter

Esmat Z. Hamdy
Actel Corporation
March 3, 2004

 Introduction

Actel is conducting ongoing investigations regarding a limited number of observed field failures of our RT54SX32S and RT54SX72S FPGAs. To date, all of the devices that we have analyzed with confirmed damage to the antifuse elements were found to have been subjected to electrical overstress (EOS). We continue to believe that our devices are reliable when used within the datasheet limits.

Some of our customers believe that the cause of these failures has not yet been properly identified. Because of this, our detailed investigation to identify the root cause is continuing. We are aware that reliability is a major factor in the selection of devices for space flight applications and are committed to resolving these open issues. Several of our Space customers have been very actively involved in the ongoing investigations, and we appreciate their assistance.


Actel Advisory Letter and Background Information on the Actel SX-S Antifuse

 Contents
  • Advisory Letter
  • Background Information


On-State Reliability of Amorphous Silicon Antifuses

Zhang, G. King, Y. Elfoukhy, S. Hamdy, E. Jing, T. Yu, P. Hu, C.

Electron Devices Meeting, 1995.
Washington, DC
pp: 551-554

zhang_95.pdf

 Abstract:
A unified model of the on-state reliability of a-Si antifuses is presented. This physical model accounts for both thermal activation and electromigration. Temperature at the conductive link is the temperature at which the antifuse is stressed and is controlled by the stress current, not the ambient. To ensure a 10 year lifetime, a-Si antifuses should be operated at a current value less than 60% of its programming current value


Time Dependent Reliability of the Programmed Metal Electrode Antifuse

R. Wong, K. Gordon, and A. Chan
International Reliability and Physics Sumposium
April 1996

wong_96.pdf

 Abstract
The programmed amorphous silicon antifuse reliability is characterized for the first time as a time dependent phenomenon.  Previously, the reliability has been characterized as a switch off or threshold behavior.  Both the dc and ac read disturb are now shown to have a time dependence.  The stress current and ambient temperature acceleration factors are discussed.


Reliability Mechanism of the Unprogrammed Amorphous Silicon Antifuse

R. Wong and K. Gordon
International Reliability and Physics Symposium
April 1994

wong_94.pdf

 Abstract
The electrical properties of the unprogrammed metal electrode amorphous silicon antifuse have been characterized.  A model is proposed for the reliability mechanism.  During a voltage stress, the leakage current through the antifuse creates localized states which increase the leakage current from 1 nA to tens of nA.  The effect eventually saturates and can be annealed out.  The amorphous silicon antifuse does not have a catastrophic failure mechanism such as the Time Dependent Dielectric Breakdown found in dielectric antifuses.  The increase in the amorphous silicon antifuse leakage current is predictable and reproducible.  The increase does not effect the reliability of the Field Programmable Gate array which uses this antifuse as a programmable interconnect.  The FPGA product has been stressed for 200 million equivalent device hours with a 7.0 volt static burn in with no failures.


Reliability Analysis of Programmed UTMC PROMs Following Post-Program Conditioning

Joseph M. Benedetto
1998 MAPLD International Conference
Greenbelt, MD, September 1998

pcd6.htm

Abstract
     Life test data were obtained on the UTMC Microelectronic Systems 64K and 256KBit programmable read-only memories (PROMs) following post-program conditioning (PPC). PPC is used to enhance the reliability (and radiation tolerance) of the UTMC PROMs following programming. To date, the life-test data show a mean time to failure (MTTF) for the 64K PROM of 1,476 years and a MTTF of 369 years for the 256K PROM (using a 60% confidence limit at 55° C). Data collection is continuing and updated reliability numbers will be published, as they become available.
     The UTMC Microelectronic Systems (UTMC) 64K and 256K programmable read-only memory (PROM) uses an amorphous silicon (a -Si) based antifuse. In the unprogrammed state the antifuse has a high resistance, typically >109W . Following programming with a series of voltage pulses, a low resistance filament is created. The UTMC PROMs use a 2-transistor/2-antifuse structure for each cell. Following programming, each cell has one programmed (low-resistance) antifuse and one unprogrammed (high-resistance) antifuse. For reliable operation, therefore, the programmed antifuse must stay in a low resistance state and the unprogrammed antifuse must stay in a high resistance state for the life of the product.
    The reliability of the unprogrammed antifuse structures were determined through a design of experiments (DOE) approach which used accelerated voltage stressing to calculate a failure rate. To determine the reliability of the programmed antifuse a thermally activated test method was used. PROMs were programmed with an "AA55" pattern (considered a worst case test pattern for these devices), conditioned with 64 hours of unbiased bake followed by 64 hours of voltage stressing. The combination of unbiased bake and voltage stressing following programming is called post-programming conditioning (PPC). The conditioned PROMs were then subjected to an extended life test at 150° C with a 5.5V dynamic stress pattern. The details of the PPC followed by the life-test results are discussed in the final paper


Conducting Filament of the Programmed Metal Electrode Amorphous Silicon Antifuse

R. Wong and K. Gordon
International Electron Devices Meeting
December 1993

gordon_93.pdf

 Abstract
Antifuses in PROM and FPGA applications have used silicon and/or polycrystalline silicon electrodes.  Metal electrode antifuses have the lowest resistance and lowest capacitance among programmable interconnect structures.  The ViaLink, a metal electrode amorphous silicon antifuse, has been used as a programmable interconnect device for a FPGA.  This paper describes for the first time, the composition, structure, electrical characteristics, and temperature dependence of the conducting filament in the programmed TiW electrode amorphous silicon antifuse.


Characterization and Modeling of a Highly Reliable Metal-to-Metal Antifuse for High-Performance and High-Density Field Programmable Gate Arrays

Chih-Ching Shih; Lambertson, R.; Hawley, F.; Issaw, F.; McCollum, J.; Hamdy, E.; Sakurai, H.; Yuasa, H.; Honda, H.; Yamaoka, T.; Wada, T.; and Chenming Hu;

Reliability Physics Symposium, 1997.
pp. 25 -33

shih_97.pdf
Synopsis

 Abstract
Reliability of a new amorphous silicon/dielectric antifuse is characterized and modeled.  Unprogrammed antifuse leakage and time-to-breakdown are functions not only of applied voltage but also of stressing polarity and temperature.  Both breakdown and leakage criteria are used to investigate their effects on time-to-fail.  A thermal model incorporates the effects of programming and stress currents, ambient temperature, and variation of antifuse resistance with temperature.  Measured temperature dependence of antifuse resistance is for the first time used to derive key physical parameters in the model.
BNL_08_01_SX72S_MEC_Damage.htm Latchup and Antifuse Hardness Test of the RT54SX72S, BNL August, 2001.   (October 29, 2001)
QL3025TempRun1.pdf Sample Icc vs. Temp Characteristics of the QL3025 Metal to Metal Antifuse FPGA
Note the exponential relationship.   (.pdf 12 kbytes).
RT54SX16TempRun1Final.pdf Sample Icc vs. Temp Characteristics of the RT54SX16 Metal to Metal Antifuse FPGA
Note the linear relationship.   (.pdf 12 kbytes).
AntifuseRuptureData_BNL0298.pdf Antifuse Heavy Ion Rupture Data (preliminary) from BNL 02/98 Test Date on Production RH1020 (90A lot split) and experimental RH54SX16, RT54SX16, and 54SX16.   Experimental RT54SX16 antifuse shows rad-hard capabilities in all tests to date.   Note that antifuse designs for these experimental parts are not yet finalized; this work will continue with additional tests over the next several months.  (.pdf 8 kbytes)
BNL0598_RH1020_
AntifuseReport.PDF		 Summary of Heavy Ion Test on the Actel RH1020 Antifuse at BNL, May, 1998.  Two units of the RH1020 showed antifuse hardness to 6.0 Volts at Bromine.  (.pdf 14 kbytes).
BNL0598_RT54SX16_
AntifuseReport.PDF		 Summary of Heavy Ion Test on the Actel RT54SX16 (prototype) Antifuse at BNL, May, 1998.  Four units of the RT54SX16 (prototype) showed antifuse hardness to 4.0 Volts at Gold (LET = 82.6 MeV-cm2/mg.  (.pdf 4 kbytes).
RHSX Antifuse Data BNL1198.htm Summary of Heavy Ion Test on the Actel RH54SX16 (prototype) Antifuse at BNL, November, 1998.  Two different antifuse "recipies" were tested, with one recipe hard at LET=60 MeV-cm2/mg with Vcore=4.4 volts.   Note that this is a 3.3 VDC device.
A1425A_BNL1198.htm A heavy ion test was conducted at Brookhaven National Labs in November, 1998.  Four A1425A devices were screened for single event latchup (SEL) and antifuse rupture.  No failures were detected.
A54SX32_Antifuse_BNL0499.htm A54SX32 prototype devices (two lot splits based on antifuse "recipe") were tested for antifuse rupture.
Test_BNL0900_SX-A_UMC.htm LAN37xx, A54SX32A Prototype, SEE/Antifuse test.  0.22 µm, UMC die.  BNL, September, 2000. (September 12, 2000)
BNL_08_01_SX72S_MEC.htm First test of the RT54SX72S (K-Latch) at BNL, August, 2001.  S/N LAN6201, LAN6202.

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