NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

SEU Performance Summary of AX1000 (non-hardened) FPGA

 

Basic Test Device Characteristics

Device
AX1000
Manufacturing Technology
0.15 µm CMOS, 7 layer metal
Foundry
UMC
Substrate
Bulk Silicon
Power Supply (Vcci/Vcca)
2.5V, 3.3V/1.5V
Number of Antifuse Switches
29,000,000
Number of I/O Banks
8
Number of Logic Tiles
9
Number of C-Cells
12,096
Number of R-Cells
6,048
Number of SRAM Bits
165,888 (9x18,432)

 

Raw Data


Note: CLU denotes "control logic upset"

 

User Flip-Flop Graphs

Cross-Section vs. LET
Data Pattern Checkerboard Ones Zeros

The AXS radiation-tolerant version will use a TMR-based
K-Latch-based flip-flop taken from the RT54SX-S

 

Embedded SRAM Graphs

 

Other SEE Effects

Clock Upset Detected
Control Logic Upsets Detected
Latchup No SEL for LET up to 119.5 MeV-cm2/mg.
Antifuse Rupture
  • No SEDR for LET up to 59.8 MeV-cm2/mg.
  • Au ion was not used because the 7-layers metal in the device would attenuate the beam to an unknown quantity.

 

Reference

"Single Event Upset and Hardening in 0.15 µm Antifuse-Based Field Programmable Gate Array," J.J. Wang, Member, IEEE, B. Cronquist, Member, IEEE, J. McCollum, S. Wolday, W. Wong, R. Katz, and I. Kleyner, to be presented at the 2003 Nuclear Space Radiation Effects Conference, Monterey, California, July 2003

Home - NASA Office of Logic Design
Last Revised: July 21, 2003
Digital Engineering Institute
Web Grunt: Richard Katz
NACA Seal