Test Date: May, 1997
Test Location: Brookhaven National Laboratory
Test Device: A32200DX, TD32200 Pattern
Lot Codes: ACQ03818.1/456157, ACQ06719.1/497634
The A32200DX is part of the Actel Integrator Series of FPGAs that consists of the A1200XL products as well as the A3200DX products. The A1200XL devices are derived from and share a user architecture with the more familiar A1200A series parts, such as the A1280A which has been heavily tested by NASA and the aerospace industry. The A3200DX family shares the same C-Module and S-Module 'logic diagram' with the A1200 series; the I/O-Module structures are also similar but differ with the addition of JTAG 1149.1 capability in some A3200DX products.
The A3200DX family introduces new architectural features. These include larger capacity (higher gates available, wide fan-in decode modules, dual-port SRAM, higher I/O counts, IEEE JTAG 1149.1 support, and 4 low-skew quadrant clocks.
The DUT design used for this evaluation is called the TD32200 and was originally intended for total dose testing of this device. It includes the usual test structures such as flip-flops, gates, counters, shift registers, etc. Additionally, it utilizes the quadrant clocks and the SRAM bits. The design has a built-in-test (BIT) capability for the SRAM where different patterns are successively written to and read back/checked from the SRAM. Internal monitors are available showing that the BIT is running and error pulses are output whenever a SRAM error is detected. This design pattern had the JTAG feature enabled.
The test set consisted of a custom test fixture which provided the ability to start/stop clocks, reset the device, test all functions, provide monitors and output error pulses. During a SEE run, the error monitor is run into a counter; after a test run, the entire functionality of the DUT is verified. Additionally, strip charts are made of ICC vs. time.
For this test, the DUT is packaged in a PQFP208 package. The device has a 10 um epi-layer, common to all Actel commercial and military devices. These samples, from two different date codes, were manufactured at the Chartered foundry.
Initial exposures used 290 MeV Bromine, with an LET of 37 MeV-cm2/mg and a range of 37.3 mm with normal incidence. All 4 runs with S/N 001 appeared to latch with high currents. The average latchup cross section was > 3.7x10-5 cm2. S/N 002 behaved similarly. A sample strip chart of ICC vs. time is shown in Figure 1, below. S/N 001 was also exposed to 265 MeV Nickel, with a LET of 27 MeV-cm2/mg and a range of 42.2 um with normal incidence. The device quickly latched.
The initial suspect for the cause of latchup was the SRAM modules; this is the key new technology that is in the A3200DX family. Previous SEE testing on the A1200XL series (both 0.6 and 0.8 um) showed no sign of latchup. An examination of the SRAM circuit layout did show that there were no guard rings. The next round of tests will include the same TD32200 pattern with the JTAG circuitry disabled and a similarly configured A32140DX; this device does not have the SRAM modules. Lastly, the failed DUTs have been sent to failure analysis for verification of epi-layer thickness.
Last Revised: February 03, 2010
Digital Engineering Institute
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