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TDSX32CQ256 DUT Design

Designer Status Report

TDSX32CQ256_1.gif

TDSX32CQ256_2.gif

TDSX32CQ256_3.gif

TDSX32CQ256_TA161.gif

TDSX32CQ256_4.gif

TDSX32CQ256_5.gif

TDSX32CQ256_6.gif

TDSX32CQ256_7.gif

TDSX32CQ256_TA161.gif

TDSX32CQ256_8.gif

TDSX32CQ256_9.gif

TDSX32CQ256_SR34.gif

TDSX32CQ256_10.gif

TDSX32CQ256_BUF50.gif

TDSX32CQ256_11.gif

Status Report

Designer Advantage R1-2000
Version: 4.0.3.5
File Name: H:\Designs\TDSX32CQ256\TDSXCQFP256.adb
Design Name: tdact3sxcq Design State: layout

Device Data

Family: 54SX Die: RT54SX32 Package: 256 CQFP
Speed: STD Voltage: 3.3
Restrict JTAG Pins: YES
Restrict Probe Pins: YES
Restrict JTAG Programming Pins: UNSET
Junction Temperature Range: MIL
Voltage Range: MIL

CAE Variables

Netlist File Name: F:/Designs/TDSX32CQ256/tdact3sxcq.edn

Fuse Variables

Fuse File: N/A
Fuse Checksum: UNSET
Pin Checksum: c630693b_1b360cdf
Silicon Signature: UNSET

Post-Combiner device utilization:

SEQUENTIAL Used:   1042   Total: 1080 (96.48%)
COMB Used:         1777   Total: 1800 (98.72%)
LOGIC Used:        2819   Total: 2880 (97.88%) (seq+comb)
IO Used:             90    Total:  221
CLOCK Used:           1    Total:    2
HCLOCK Used:          1   Total:     1

There were 0 error(s) and 5 warning(s) in this design. 

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Last Revised: January 09, 2002
Digital Engineering Institute
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