BNL May 20th, 2002 Test Results - RT54SX32S Rev 2 and RT54SX72S Rev 1
May 28, 2002
J.J. Wang
(408) 522-4576 jih-jong.wang@actel.com
I. Summary
The goal is to verify that the changes in the new mask revision for both the RT54SX32S or RT54SX72S do not affect their SEE (single event effects) performance. The previous revisions of mask-sets of these two devices are very SEE hard. The only design-change that has any SEE implication is the redesign of the hardwired TRSTB pin in the revision-2 32S. To verify this redesign, a heavy-ion-beam test with LET (linear energy transfer) above 20 MeV-cm2/mg shall be sufficient to detect the effect of the hardwired TRSTB pin. Test data show that the LET threshold required to invoke the relevant single event abnormality (JTAG upset) is well below 20 MeV-cm2/mg. The susceptibility increases with lower bias (VCC). Bromine ion with sufficient LET was chosen to perform the test. For completeness, the new revisions for both 32S and 72S are tested. The results show that, as expected, the redesign for both the 32S or 72S has no detectable impact on single event effects.
A. DUT and Testing Condition
Table 1 lists the DUT and testing condition.
Table 1
Device |
RT54SX32S |
Foundry/Technology |
MEC/0.25 µm |
Wafer Lot # |
T25JS001 |
Package |
CQ256 |
Serial Number |
WAN7702, WAN7703 |
Beam Facility |
Brookhaven National Lab |
Design |
TMRSX32_CQ256_HCLK |
Total number of flip-flops |
800 user flip-flops |
Input Pattern |
Checkerboard |
Frequency |
1 MHz |
Special Treatment |
Removed top polyimide |
Testing Temperature |
Room |
B. Test Results
Single event latch-up (SEL), single event dielectric rupture (SEDR), clock upset, or JTAG upset was not detected in any run.
The test data are listed in table 2. The statistical distribution of these errors indicates that they are SET induced. Note that (see Appendix at the end of this report) DOC and DOS sample 100 bits each, and 1_ERR and 0_ERR 300 bits each. DOVH and DOH have user-level-TMR bits. Statistically, SEU bit-errors of DOC/DOS should be approximately one third of 1_ERR/0_ERR and many orders of magnitude larger than that of DOVH/DOH. NASA website,
http://klabs.org has data on previous version and some more analyses.Table 2
Run |
DUT S/N |
Ion |
LET(Si) MeV-cm2/mg |
Tilt deg |
Roll deg |
Bias VCCI/VCCA |
Fluence #/cm2 |
1_ERR |
DOC |
DOVH |
DOS |
DOH |
0_ERR |
15 |
7702 |
Br-81 |
43.1 |
30 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
0 |
0 |
0 |
0 |
0 |
16 |
7702 |
Br-81 |
52.8 |
45 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
0 |
0 |
0 |
0 |
0 |
17 |
7702 |
Br-81 |
58.1 |
50 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
0 |
1 |
0 |
0 |
1 |
18 |
7702 |
Br-81 |
58.1 |
-50 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
1 |
1 |
1 |
0 |
0 |
19 |
7702 |
Br-81 |
37.3 |
0 |
0 |
5.5/2.75 |
1.00E+07 |
0 |
0 |
0 |
0 |
0 |
0 |
20 |
7703 |
Br-81 |
37.3 |
0 |
0 |
4.5/2.25 |
1.03E+07 |
0 |
0 |
0 |
0 |
0 |
0 |
21 |
7703 |
Br-81 |
52.8 |
45 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
0 |
1 |
2 |
0 |
0 |
22 |
7703 |
Br-81 |
58.1 |
50 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
0 |
1 |
0 |
0 |
0 |
23 |
7703 |
Br-81 |
58.1 |
-50 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
1 |
0 |
1 |
0 |
0 |
24 |
7703 |
Br-81 |
37.3 |
0 |
0 |
5.5/2.75 |
1.00E+07 |
0 |
0 |
0 |
0 |
0 |
0 |
A. DUT and Testing Condition
Table 3 lists RT54SX72S DUT and testing condition.
Table 3
Device |
RT54SX72S |
Foundry/Technology |
MEC/0.25 µm |
Wafer Lot # |
T25KS005 |
Package |
CQ256 |
Serial Number |
WAN7802, WAN7803 |
Beam Facility |
Brookhaven National Lab |
Design |
TMRSX72_CQ256_HCLK |
Total number of flip-flops |
800 user flip-flops |
Input Pattern |
Checkerboard |
Frequency |
1 MHz |
Special Treatment |
Removed top polyimide |
Testing Temperature |
Room |
B. Test Results
Single event latch-up (SEL), single event dielectric rupture (SEDR), clock upset, or JTAG upset was not detected in any run.
Table 4 shows the details of the test data. Again, the statistical distribution of errors indicates that they are SET induced.
Table 4
Run |
DUT S/N |
Ion |
LET(Si) MeV-cm2/mg |
Tilt deg |
Roll deg |
Bias VCCI/VCCA |
Fluence #/cm2 |
1_ERR |
DOC |
DOVH |
DOS |
DOH |
0_ERR |
25 |
7802 |
Br-81 |
37.3 |
0 |
0 |
5.5/2.75 |
9.98E+06 |
0 |
0 |
0 |
0 |
0 |
0 |
26 |
7802 |
Br-81 |
37.3 |
0 |
0 |
5.5/2.75 |
1.00E+07 |
0 |
0 |
0 |
0 |
0 |
0 |
27 |
7802 |
Br-81 |
52.8 |
45 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
1 |
0 |
0 |
0 |
0 |
28 |
7802 |
Br-81 |
37.3 |
0 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
0 |
0 |
0 |
0 |
0 |
29 |
7802 |
Br-81 |
58.1 |
50 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
0 |
0 |
0 |
0 |
0 |
30 |
7802 |
Br-81 |
58.1 |
-50 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
0 |
0 |
0 |
0 |
0 |
31 |
7803 |
Br-81 |
37.3 |
0 |
0 |
5.5/2.75 |
1.01E+07 |
0 |
0 |
0 |
0 |
0 |
0 |
32 |
7803 |
Br-81 |
37.3 |
0 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
0 |
0 |
0 |
0 |
0 |
33 |
7803 |
Br-81 |
52.8 |
45 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
1 |
0 |
2 |
0 |
0 |
34 |
7803 |
Br-81 |
58.1 |
50 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
0 |
0 |
0 |
0 |
0 |
35 |
7803 |
Br-81 |
52.8 |
-45 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
0 |
0 |
1 |
0 |
0 |
36 |
7803 |
Br-81 |
43.1 |
-30 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
0 |
0 |
0 |
0 |
0 |
37 |
7803 |
Br-81 |
43.1 |
30 |
0 |
4.5/2.25 |
1.00E+07 |
0 |
0 |
0 |
0 |
0 |
0 |
Appendix TMRSX32 and TMRSX72 Pattern for SEU Testing
PROGRAMMABLE TECHNOLOGIES WEB SITE
A scientific study of the problems of digital engineering for space
flight systems,
with a view to their practical solution.
TMRSX32 Pattern
Used for SX and SX-A and SX-AS Testing
Summary
The TMRSX32 pattern is one of the patterns used for SEE testing of the SX32-series of FPGAs. It has been used in the SX, SX-A, and SX-AS prototypes and products, both "RT" and "A" versions.
This pattern also has some capability for performance and TID testing, although primarily not designed for that use. The "TDxx" series of patterns is optimized for total dose testing. This TMRSX32 pattern can, however, give a quick look at total dose performance.
This pattern is independent of the implimentation of individual flip-flops in the silicon. For example, an RT54SX32-AS, which has TMR-based flip-flops in the silicon, will have 9 flip-flops total for a TMR module constructed at the user level. For the sake of synplicity [not the software package] and practical value, all flip-flops, regardless of implementation [so far ranging from 1-3], will count as a single flip-flop. If this test pattern is modified for use in the RT54SX32-AS or other similar devices, it will be given a new pattern name.
Test Pattern Description Overview
The primary section of the TMRSX32 pattern consists of 4 shift registers, all clocked by a common clock pin. Each shift register design is different, to measure different aspects of the architecture. The length of each shift register is 100 stages, although more then one flip-flop is used for a stage in two of the designs, in addition to some extra logic.
Facilities for performance and total dose testing will be discussed.
SEE Test Facilities
Clocking
The CLKBUF is used to drive the global clock and is available off-chip for external monitoring. No provisions are made to satisfy tH other than the normal place and route algorithms. That is, there are no buffers intentionally added between flip-flops to increase delays. There are some buffers added in some shift registers, for example, to measure SETs.
MSOFT0A Shift Register
This 100-stage shift register is composed of DF1 R-Cell elements, each of which is separated by a BUFF. Each BUFF has a PRESERVE attribute attached to its output to ensure that the Combiner does not eliminate this "unnecessary" logic. Since the BUFF has a fanout of 1, it permits the fastest type of connection, a Direct Connect. The Direct Connect is a horizontal routing resource that provides connections from a C-cell to its neighboring R-cell in a given SuperCluster. DirectConnect uses a hard-wired wignal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns.
NOTE: SINCE THE CHIP WAS RELAID OUT IN A HURRY FOR A CHANGE OF PACKAGE FOR THIS TEST, WE MUST GO BACK AND VERIFY THAT DIRECT CONNECTS WERE SUCCESSFULLY USED.The output of this shift register is DOC.
MSOFT0 Shift Register
This shift register is identical to the MSOFT0A shift register described above except that there are no BUFFs separating the shift register elements. It is composed of 100 DF1 R-Cell elements.
The output of this shift register is DOS.
MHARD0A Shift Register
This 100-stage shift register is composed of TMR-hardened [at the user level] flip-flops modified to detect SETs. Each of these TMR-hardened elements consists of three DFPCB flip-flops and two MX4 muxes and an INV inverter. The first mux functions as a majority voting element. The second MX4 and the INV functions as a disagreement detector. The outputs of all disagreement detectors for this register are logically OR'd.
Each TMR-hardened triplet has been modified by the use of additional BUFF and INV elements. The INV's input is grounded and the output is connected to the CLR* inputs of each of the three DFPCB flip-flops. Similarly, the input of the BUFF is tied to VCC and its output is connected to the three PRE* inputs of the three flip-flops. Any hit on either the INV or the BUFF would be "caught" by the flip-flops. This may result in a combination of logic errors or activation of the disagreement detector, depending on how many of the flip-flops were effected by the SET.
The output of the shift register is DOVH. The output of the OR'd disagreement detectors is 0_ERR.
MHARD0 Shift Register
This 100-stage shift register is composed of TMR-hardened [at the user level] flip-flops. Each of these TMR-hardened elements consists of three DFPCB flip-flops and two MX4 muxes and an INV inverter. The first mux functions as a majority voting element. The second MX4 and the INV functions as a disagreement detector. The outputs of all disagreement detectors for this register are logically OR'd.
The output of the shift register is DOH. The output of the OR'd disagreement detectors is 1_ERR.
This leads to 100 + 100 + 300 + 300 = 800 flip-flops for this design.
Performance and TID Test Facilities
Toggle Rate
The HCLKB is tied to the clock input of a TF1A toggle flip-flop and is brought of chip. The input pin is XHCLK and the output pin is XQOUT.
Asynchronous Count Rate
An INBUF is connected to the clock input of a RIP8 ripple counter soft macro. The most significant bit [divide by 256] is brough off chip. The input is XRIPIN and the output is XRIPOUT.
Logic Path Delay
An INBUF is connected, in series, to 100 BUFF elements and is brought off chip. The inputs is XLOGICIN and the output is XLOGICOUT. Add BUFF elements have been PRESERVE'd.
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