Test and DUT breakdown
LAN4801 kamikaze
LAN4802 - kamikaze, "4STRINGS" pattern. [all others older TD pattern]
LAN4803 kamikaze with "mountJJ" - Spare global clock input not terminated.
LAN4804, LAN4805 production:
- "parafunctested"
- irradiated to ~100 krad @10krad/day
- "parafunctested"
LAN4806, LAN4807 production-turned-kamikaze:
- "parafunctested"
- irradiated to ~65 krad @24krad/day
- "parafunctested"
- irradiated again (by accident!) for ~90 krad until functional failure
All devices while irradiated are subjected to basic functional and parametric (propagation delay) test approximately once per hour
DUT Patterns
All devices, except for LAN4802 used the TDSX32CQ256_DUT pattern. LAN4802 used the TD_4Strings_SX32_DUT pattern.
Pre-Irradiation Irregularities
Safe power-up/power-down of the I/O's could not be verfied. The verification effort failed. Some of the parts had a DC current on VCCI of over 10 mA, until power was applied to VCCA. These parts were not used for testing of LAN4804 through LAN4807; "cherry-picked" parts were used, with the VCCI currents of a few mA, prior to the application of VCCA.
Post-Irradiation Irregularities
LAN4804 and LAN4805 lost functionality as a result of power-up/power-down sequence after irradiation, with ICCA on both DUTs exceeding 500 mA. After more than 24 hours of "annealing" and repeated applications of clock functionality was restored to both DUTs. ICCA values were also reduced to significantly lower values. Even after basic functionality retuned the DUTs still continued to exhibit irregular power-up/power-down behaviour, i.e. significantly varying ICCA values for every power cycling sequence.
LAN4801_sc.pdf strip chartLAN4801_bw.pdf best/worst case ICCA
LAN4803_sc1.pdf strip chart (vs. time)
LAN4803_sc2.pdf strip chart (vs. dose)
LAN4803_sc3.pdf strip chart (zoomed in)
LAN4803_bw1.pdf best/worst case (ICCA)
LAN4803_bw2.pdf best/worst case (ICCI)
LAN4803_pd.pdf prop delay
LAN4804_05_sc.pdf strip chart
LAN4804_05_ft.pdf functional
LAN4804_05_bw1.pdf best/worst case (ICCI)
LAN4804_05_bw2.pdf best/worst case (ICCA)
LAN4804_05_pd.pdf prop delay
LAN4806_07_sc1.pdf strip chart
LAN4806_07_sc2.pdf zoomed in
LAN4806_07_ft.pdf functional
LAN4806_07_bw1.pdf best/worst case (ICCI)
LAN4806_07_bw2.pdf best/worst case (ICCA)
LAN4806_07_bw3.pdf best/worst case (ICCA) zoomed in
LAN4806_07_pd.pdf prop delay
LAN4802 Charts
LAN4802_03_Array_Current_vs_Time.pdf
LAN4802_03_Array_Current_vs_rad.pdf
Propagation delays
Combinational Path - Rising Output, (ns)
Part #
LAN4804
LAN4805
LAN4806
LAN4807
pre-rad
638
649
649
641
post-rad
792
800
706
699
Combinational Path -Falling 0utput, (ns)
Part #
LAN4804
LAN4805
LAN4806
LAN4807
pre-rad
637
647
646
640
post-rad
795
799
701
689
SerialIn Path - Rising Output, (ns)
Part #
LAN4804
LAN4805
LAN4806
LAN4807
pre-rad
35
37
38
37
post-rad
40
41
40
40
SerialIn Path -Falling 0utput, (ns)
Part #
LAN4804
LAN4805
LAN4806
LAN4807
pre-rad
40
42
42
41
post-rad
48
48
46
46
SerialOut Path - Rising Output, (ns)
Part # |
LAN4804 |
LAN4805 |
LAN4806 |
LAN4807 |
pre-rad |
35 |
35 |
37 |
37 |
post-rad |
39 |
39 |
40 |
39 |
SerialOut Path Path -Falling 0utput, (ns)
Part # |
LAN4804 |
LAN4805 |
LAN4806 |
LAN4807 |
pre-rad |
40 |
40 |
41 |
41 |
post-rad |
47 |
48 |
46 |
45 |
Logic Threshold (V)
Part #
LAN4804
LAN4805
LAN4806
LAN4807
pre-rad
1.59
1.56
1.55
1.56
post-rad
1.56
1.56
1.53
1.50
Output Transition Time
Rising edge
Part #
LAN4804
LAN4805
LAN4806
LAN4807
pre-rad
post-rad
Falling edge
Part #
LAN4804
LAN4805
LAN4806
LAN4807
pre-rad
post-rad
VOH/VOL
VOH
VOL
pre-rad
post-rad
Startup Transients
Because of the parts failures, we were unable to obtain startup transient data.
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Last Revised: January 09, 2002
Digital Engineering Institute
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