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SX-A SEE Test

UMC Die, 0.22 µm

Lot Code D7766.12 WFR #15

BNL, October, 2000

Summary

This is a test of the SX-A, 0.22 µm, UMC die.  This test was run with minimal supply voltages, 4.5/2.25/2.25 for most runs.  Higher voltages were used for SEL and antifuse rupture tests. It used the the TMRSX32_Pattern logical pattern. 

Package: CQFP256

Serial Nos. LAN4001, LAN4002

Test frequency: 1 MHz.

DUT schematics:  TMRSX32_Logic.ppt.

Total Number of Flip-flops: 800 (user flip-flops).

Clock Configuration: CLK

Ions used:

210 MeV Cl-35

284 MeV Br-81

345 MeV I-127

Antifuse rupture: not detected.

SEL: not detected.

Loss of control, i.e., JTAG upset: Detected.  Part believed not to be correctly programmed.

Test Data

Analysis

Preliminary findings:

SEU upset cross-section curve.  LAN400xSEU.pdf

The flip-flop strings come in two pairs.

The first pair, DOC and DOS, show little difference in SEU rates.  The difference between these pairs is that the DOC shift register has a buffer between each shift register stage.  In the SX/SX-A architecture, this leads to the use of a direct connect (in most cases, since the fanout from the C-Cell to the R-Cell is one) which would have the least capacitance, as compared to a fast connect (1 antifuse) and a regular connection (2 or more antifuses).  There may be some residual upset rate from the use of C-Cells and fast connect but can not be seen at the frequencies tested so far.  See ../../../SEU_Hardening/Test_BNL0800.htm for some frequency test data.  It is planned to have a high-speed board built to further explore this area.

The second pair of circuits are the two TMR-hardened strings.  Both of these strings are hardened at the user level and not at the device level.  There were no detected errors on DOH.  DOVH differs from DOH, however, in that buffers are used to bias the presets and clears of the flip-flops and not tie-offs to a voltage rail. This SET detector is more sensitive than the one above since the asynchronous inputs to the flip-flop will catch and hold any transient of sufficient width to flip a memory element.   For the DOC/DOS strings, the glitch must be caught at a clock.  However, the DOC string results in the buffer having a fan out of one, so a worst-case direct connect (0 antifuses) can be used - the place and route software will be given the goal of using direct connects for each of the buffers in between sequentially adjacent flip-flops.   For the UMC 0.22 um SX-A FPGA, this can not be done for the DOVH string, since there must be a fanout of three for each buffer biasing either the preset or clear inputs.   Obviously, if the fan out was reduced to one, this would maximize the number of SETs but make the number of errors from the TMR-hardened strings unchanged from the baseline version, since the upset would be voted out.  However, the errors would be picked up on the error monitors.  Since we are gathering our preliminary data, a different version of the test chip may be built for further testing and evaluation.   Note, however, that the primary application of presets and clears for R-Cells use a rather heavy load, as most (but not all!) designs use this function for power-on initialization, and not "normal," operating logic.  Some circuit applications like synchronizers often do make use of this input to clear out an incoming asynchronous signal.

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Last Revised: January 09, 2002
Digital Engineering Institute
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