| 1. | US04956814 | 09/11/1990 | Memory cell with improved single event upset rate reduction circuitry |
| 2. | US04797804 | 01/10/1989 | High density, high performance, single event upset immune data storage cell |
| 3. | US05525923 | 06/11/1996 | Single event upset immune register with fast write access |
| 4. | US05053848 | 10/01/1991 | Apparatus for providing single event upset resistance for semiconductor devices |
| 5. | US04914629 | 04/03/1990 | Memory cell including single event upset rate reduction circuitry |
| 6. | US04912675 | 03/27/1990 | Single event upset hardened memory cell |
| 7. | US05657267 | 08/12/1997 | Dynamic RAM (random access memory) with SEU (single event upset) detection |
| 8. | US05315544 | 05/24/1994 | Radiation-hardened memory storage device for space applications |
| 9. | US05204990 | 04/20/1993 | Memory cell with capacitance for single event upset protection |
| 10. | US05504703 | 04/02/1996 | Single event upset hardened CMOS latch circuit |
| 11. | US05418473 | 05/23/1995 | Single event upset immune logic family |
| 12. | S05406513 | 04/11/1995 | Mechanism for preventing radiation induced latch-up in CMOS integrated circuits |
| 13. | US05311070 | 05/10/1994 | Seu-immune latch for gate array, standard cell, and other asic applications |
| 14. | US05307142 | 04/26/1994 | High performance static latches with complete single event upset immunity |
| 15. | US05196734 | 03/23/1993 | CCS latch with in-circuit redundancy |
| 16. | US05175605 | 12/29/1992 | Single event upset hardening circuits, devices and methods |
| 17. | US05111429 | 05/05/1992 | Single event upset hardening CMOS memory circuit |
| 18. | US05046044 | 09/03/1991 | SEU hardened memory cell |
| 19. | US04931990 | 06/05/1990 | Hardened bubble memory circuit |
| 20. | US04852060 | 07/25/1989 | Soft error resistant data storage cells |
| 21. | US04809226 | 02/28/1989 | Random access memory immune to single event upset using a T-resistor |
| 22. | US04805148 | 02/14/1989 | High impendance-coupled CMOS SRAM for improved single event immunity |
| 23. | US04785200 | 11/15/1988 | Self correcting single event upset (SEU) hardened CMOS register |
| 24. | US05649097 | 07/15/1997 | Synchronizing a prediction RAM |
| 25. | US05331164 | 07/19/1994 | Particle sensor array |
| 26. | US5031180 | 07/09/1991 | Triple redundant fault-tolerant register |
| 27. | US04863878 | 09/05/1989 | Method of making silicon on insalator material using oxygen implantation |
| 28. | US04786865 | 11/22/1988 | Method and apparatus for testing integrated circuit susceptibility to cosmic rays |
| 29. | US05341009 | 08/23/1994 | Fast charging MOS capacitor structure for high magnitude voltage of either positive or negative polarity |
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Last Revised: January 09, 2002
Digital Engineering Institute
Web Grunt: Richard Katz