NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

The PLL and Prototyping RTAX-S FPGAs

Introduction

AX series devices are often used for prototyping circuits that ultimately will fly using the RTAX-S series FPGAs.  While there are a number of significant differences between AX and RTAX-S, this application note will address the PLL present in the AX and it's impact on prototyping RTAX-S systems.

Discussion

First note the figure below, from the Axcelerator Family FPGAs data sheet, the power supply connections for the PLL.  One of eight circuits for each device is shown.

Power supply connections for AX series devices.  There are eight in each device.

For the RTAX-S series FPGAs, the PLL's are not present in the silicon and the corresponding power and compensation pins are "no connects."  From the Actel application note titled "Differences Between RTAX-S and Axcelerator," we have the following:

All eight PLLs that are included in Axcelerator are NOT part of RTAX-S. The corresponding PLL supply voltage pins (VCCPLX and VCOMPLX) have become No Connects (NC). These pins are not connected to any circuitry in the device and can be driven to any voltage or left floating with no effect on the operation of the device.

So, for flight systems, the PLL connections can be ignored.  But these connections can not be ignored for any AX devices that are used for prototyping.  From the AX data sheet we have the following two paragraphs:

VCCPLA/B/C/D/E/F/G/H Supply Voltage

PLL analog power supply (1.5V) for internal PLL. There are eight in each device. VCCPLA supports the PLL associated with global resource HCLKA, VCCPLB supports the PLL associated with global resource HCLKB, etc. The PLL analog power supply pins should be connected to 1.5V whether PLL is used or not.

VCOMPLA/B/C/D/E/F/G/H Supply Voltage

Compensation reference signals for internal PLL. There are eight in each device. VCOMPLA supports the PLL associated with global resource HCLKA, VCOMPLE supports the PLL associated with global resource CLKE, etc. The VCOMPLX pins should be left floating if PLL is not used.

Also note that in the figure above, the 250 Ω resistor as well as the 10 µF and 0.1 µF capacitors are solely for noise filtering to support PLL operation.

Recommendations

Based on the discussion above, the following are recommended practices for flight systems that will use AX series FPGAs for prototyping:

  1. All VCCPLX pins should be connected to the 1.5V supply
  2. All VCOMPLX pins should be left floating
  3. The resistors and capacitors associated with the PLL for the AX FPGA can be deleted.

 

RTAX-S and AX Application Notes

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Last Revised: November 27, 2005
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