The RTAX-S series of FPGA provides higher density devices than the previous RTSX-SU devices.  This application note provides tables to permit estimates to be made of the logic densities of these new devices.  It is clear that the device number scheme does not present an easy to use metric for estimating logic capacity.

The two tables below show both in absolute and relative terms the logic capacities of the RTSX-SU and RTAX-S families.  Data in Table II is normalized to the RTSX-32SU.  Also note that there are some capacity improvements in the RTAX-S FPGAs that are not accounted for in the table.  This extra capacity comes from RTAX-S architectural additions relative to the RTSX-SU:

• Flip-flops in the I/O Cells (input, output, and enable registers)

• Carry chain logic

• Buffer modules in each super cluster and I/O cluster

Additionally note that each RAM block in RTAX-S consists of 4,608 bits.  There is no block RAM present in RTSX-SU.

 

Table I.  Architectural logic resources of RTSX-SU and RTAX-S

	RTSX-SU		RTAX-S
	RTSX32SU	RTSX72SU	RTAX250S	RTAX1000S	RTAX2000S	RTAX4000S1
R-Cells	1,080	2,012	1,408	6,048	10,752	20,160
C-Cells	1,800	4,024	2,816	12,096	21,504	42,840
Ram Blocks			12	36	64	120

	RTSX-SU		RTAX-S
	RTSX32SU	RTSX72SU	RTAX250S	RTAX1000S	RTAX2000S	RTAX4000S1
R-Cells	1.0	1.9	1.3	5.6	10.0	18.7
C-Cells	1.0	2.2	1.6	6.7	11.9	23.8