NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

RTAX-S Action Probe

INTRODUCTION

These notes are intended to supplement the manufacturer's material on the RTAX-S Action Probe, giving some insight and additional information.

The reference section below contains links to further documentation that also supplement the data sheet.  Note that the probing information in the RTAX-S and AX data sheets are not identical.  The information in this application note is taken from both data sheets and conversations with Actel engineers.

FOUR PROBE PINS BUT TWO PROBE POINTS PER TILE

For the RTAX-S series of devices, each FPGA now has 4 diagnostic outputs called PRA/B/C/D.  However, consider that the architecture supports at most two diagnostic outputs per tile.  Thus, the designer should consider placing modules in appropriate tiles to support planned and expected test activities.

While modules can be manually placed in different tiles to increase probe "coverage," separating nodes may increase timing delays.  One strategy to mitigate this effect is to place circuits "close" to each other near tile boundaries.

ACTION PROBE LIMITATIONS

The Action Probe has some limitations on what can be probed in the RTAX-S architecture, as listed below.  The following can not be probed:

  1. Input registers

  2. Output registers

  3. HCLK

  4. CLKBUF

Restriction 4, not being able to probe CLKBUF's, suggests that the designer should use an INBUF + CLKINT pair to source a signal onto the routed array clock distribution network.  However, since only the clock inputs are SET hardened, it is not clear that using an INBUF instead of a CLKBUF in the I/O Cell will retain the SET hardness.  This open item has been sent to Actel for resolution. 

Another approach for probing the routed array clock is to bring the clock signal on-chip using the SET hardened CLKBUF and then use a C-Cell to provide the path to the Action Probe circuits.  Ensure that the buffering logic element is not optimized out of the netlist.

 

TERMINATE SPECIAL PINS PROPERLY

The following are the special pins and must be properly terminated for reliable operation:

  1. PRA/B/C/D (Probes A, B, C, and D): Output.  Do not connect.

  2. TCK (Test Clock): No internal resistor.  Terminate to either VCCDA or ground.  Do not leave floating.

  3. TDI (Test Data Input): Internal pullup resistor.  Either do not connect or terminate to VCCDA.

  4. TDO (Test Data Output):  Output.  Do not connect.

  5. TMS (Test Mode Select): Internal pullup resistor.  Either do not connect or terminate to VCCDA.

  6. TRST (Boundary Scan Reset Pin): This pin is more complex as in RTAX-S the internal pull-up resistor, required by the IEEE JTAG standard, is optional.  It is recommended at this time, for consistency, to enable the pull-up resistor and treat this pin as in previous generation of Actel components and other IEEE JTAG compatible devices.  As such, the pin should be terminated to ground via 0 ohms, which is critical for flight safety.  This 0 ohm termination obviously needs to be removed for debugging.

 


Figure 1. Silicon Explorer terminations for RT54SX-SU.  RTAX-S terminations are similar.

 

TERMINATION RESISTORS NEEDED FOR SILICON EXPLORER INTERFACE

Similar to the RT54SX-S and RTSX-SU FPGAs, series resistors are needed between the Silicon Explorer probe and the FPGA under test (see Figure 2).


Figure 2.  On-board resistors are used to provide proper signal integrity for Silicon Explorer and RTAX-S
FPGA communications.  See Figure 1 above for proper terminations of the TCK and TRST* pins.

The following are notes on the on-board resistors from the data sheet (RTAX-S v2.1):

Actel recommends that you use a series termination resistor on every probe connector (TDI, TCK, TDO, PRA, PRB, PRC, and PRD). The series termination is used to prevent data transmission corruption (i.e., due to reflection from the FPGA to the probe connector) during probing and reading back the checksum. With an internal setup we have seen 70-ohm termination resistor improved the signal transmission. Since the series termination depends on the setup, Actel recommends users to calculate the termination resistor for their own setup. Below is a guideline on how to calculate the resistor value.

The resistor value should be chosen so that the sum of it and the probe signal’s driver impedance equals the effective trace impedance.

Z0 = Rs + Zd

Z0= trace impedance (silicon explorer’s breakout cable’s resistance + PCB trace impedance), Rs=series termination, Zd=probe signal’s driver impedance.

The termination resistor should be placed as close as possible to the driver.

Among the probe signals, TDI, TCK, and TMS are driven by Silicon Explorer. A54SX16 is used in Silicon Explorer and hence the driver impedances needs to be calculated from SX08/SX16/SX32 IBIS Model (Mixed Voltage Operation). PRA, PRB, PRC, PRD, and TDO are driven by the FPGA and driver impedance can also be calculated from the IBIS Model. Silicon explorer’s breakout cable’s resistance is usually close to 1 ohm.  [Note there is a request in to Actel to ensure that this paragraph also applies to Silicon Explorer II.  -- rk].

 

REFERENCES

  1. "An Unobtrusive Debugging Methodology for Actel AX and RTAX-S FPGAs," Jonathan Alexander, Actel Corp.  2004 MAPLD International Conference, September 2004, Washington, D.C.

  2. "IEEE Standard 1149.1 (JTAG) in the SX/RTSX/SX-A/eX/RT54SX-S Families," Actel Corporation.

  3. "Using the Silicon Explorer For System-Level Debug," Actel Corporation.

 

RTAX-S and AX Application Notes

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Last Revised: December 22, 2005
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