NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

C-C Cell Flip-Flops in SX, SX-A, SX-S

A simple circuit of one negative edge triggered flip-flop is shown below.   This should increase the LET resistance of the memory element, when compared to an R-Cell in SX and SX-A technology.  For SX-S, this is a technique that can be used to increase the number of flip-flops available.

However, data indicates that an R-Cell was used, not the pair of C-Cells, which would give the user an implementation that did not have the expected SEU tolerance.   For this example, I targeted the RT54SX32.

Informal testing showed that the mapping is incorrect for RT54SXS series devices but correct for Act 3.  I only sampled flip-flops types.  DF1C_CC was also mapped incorrectly.

Initially, I found this problem using some older software, R1-2000.   I was able to replicate this problem, targeting the RT54SX32, A54SX32A, and the RT54SX72S, using the latest software available, Libero 2.2, service pack 2, Designer 4.5.2.14. 

Designers should carefully check the implementation of their flip-flops, either from schematic-based or HDL-based designs, to help ensure that the radiation performance of their design is adequate.  Some tips are given below.

However, it appears that this is implemented as an R-Cell, not as a pair of C-Cells.

After compiling, we get the following, showing 1 sequential element used.

The Import command succeeded ( 00:00:01 )
Post-Combiner device utilization:
SEQUENTIAL Used:      1 Total: 1080 (0.09%)
COMB Used:            0 Total: 1800 (0.00%)
LOGIC Used:           1 Total: 2880 (0.03%) (seq+comb)
IO w/ Clocks Used:    3 Total:  169
CLOCK Used:  0 Total: 2
HCLOCK Used: 0 Total: 1

Taking a look in ChipEdit, we see how the chip is physically configured, with the flip-flop implemented in an R-Cell.

We can also see what we get from the flip-flop report:

********************************************************************
                              FF Report
********************************************************************

Designer Advantage R1-2000
Version: 4.0.4.4
Date: Mon Nov 04 20:26:35 2002
Design Name: test_cc Family: 54SX Die: RT54SX32 Package: 208 CQFP

Type Library name Macro name
------- -------------------- ----------

Seq DF1B_CC $1I4

Total
-----
1 Seq
0 CC

Again, we see that we have what was thought to be a C-C Cell flip-flop implemented as an R-Cell.

Here is a summary chart of the performance difference between the two types of flip-flops, obtained with an experimental C-C Cell flip-flop design.

Heavy Ion Test Results

Experimental Flip-Flop Design

Looking at the library guide for the R1-2000 software, we find the following:

As we can see, the documentation claims that the flip-flops are implemented with two C-Cells.  This is an error, as this flip-flop was designed for migration purposes from pre-SX families, but will not give the desired radiation performance.  This can be seen in the updated library guide, below.

Here we see that in the SX, SX-A, and SX-S series devices, the macro is implemented in one R-Cell, as opposed to two C-Modules n the earlier familes.

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