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February 28, 2006. |
Overview: |
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Introduction |
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March 2005 |
Introduction This technical brief provides programming information and clarification of common questions regarding the programming of Actel RTSX-S (MEC fabricated) and RTSX-SU (UMC fabricated) devices. This document is intended for users performing RTSX-S and/or RTSX-SU device programming only. |
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Overview Recently one project had a condition where input levels were not at a good logic level and anomalous ICCI currents were observed. Based on previous results, it was expected that delta ICCI values should be on the order of 1 mA/input. The currents observed in the system under test represented current levels per pin of more than an order of magnitude higher. Since the previous values were based on older families and a simulation of the RT54SX-S FPGAs, a sample pin was chosen on an available RTSX32SU device. The results are presented below. |
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December 22, 2004 |
Synopsis This notice is to inform you that following the qualification of the RTSX-SU product family, Actel has made a single mask change to improve manufacturing yields. Qualification was conducted and has validated that the change still meets the applicable released technical specifications. Therefore, the RTSX-SU product family remains unchanged in form, fit, functionality, and reliability. The affected devices are RTSX32SU and RTSX72SU with all speed and package combinations. |
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July 18, 2004. |
Abstract During the development of flight hardware, it was suggested that outputs in a particular design be switched to low slew since high slew drivers were not needed. Since the first unit was already built with high slew drivers, the second unit, on an identical circuit board, was built with low slew drivers. Data was obtained (see below) and the project engineers decided to retrofit the first unit with low slew drivers. |
June 22, 2004 |
Recommendations
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Overview The enclosed chart shows aggregate data from multiple lots of RT54SX72S FPGAs, totalling 1,040 individual devices. The speed data, with a mean delay of 73.8 ns, is measurements of the binning circuit, which is representative of logic paths and is used in determing device speed grade. Note that the delays over life do not necessarily "track," as there are both differences in the changes of delay as well as some differences in the sign of a delay change. |
May 17, 2004. |
Synopsis (excerpt) Actel Corporation has developed a new programming algorithm for the SX-A and RTSX-S devices built in the 0.25 µm MEC/Tonami process, scheduled for release in May, 2004. Their internal testing and qualification effort has, to date, produced no detected failures in over 800 devices. It is noted that devices programmed with the old programming algorithm and subjected to the same electrical environment, failed at a rate of approximately 2.5%. An "Industry Tiger Team," led by The Aerospace Corporation, will evaluate SX-S series devices programmed with the old algorithm. This approach is dictated by Aerospace Corporation management and is based on certain programs' desire to rationalize using existing hardware "as is." In light of the above, the NASA Office of Logic Design will evaluate SX-S series devices programmed with the Actel's new algorithm. This independent NASA activity is endorsed and sponsored by the NASA Engineering and Safety Center. |
March 25, 2004 |
Summary This advisory is to inform the users of the Designer software version 5.1 and prior versions that when creating designs containing both QCLK Buf and QCLK Int macros for the A54SX72A and RT54SX72S devices, functional time zero failures may result. These failures are immediate; any designs that have passed initial functional test do not have these problems. |
NA-GSFC-2004-06 |
Actions Recommended: All relevant personnel should ensure that all specifications, manufacturer’s guidance, and good engineering practices are always followed and conservative design practices should be employed; failure to follow such an approach appears to correlate with device failure. |
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Synopsis Eleven FPGAs in the SX-A and RTSX-S series, built in the 0.25 µm MEC/Tonami process have had confirmed programmed antifuse failures to date during user testing. No failures have been reported with 0.22 µm SX-A or eX series devices. For the failures observed in 0.25 µm MEC/Tonami process devices, at least one of the following applies:
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| Introduction Many modern CMOS digital microcircuits have very strong drivers; the device characteristics have changed over the years. Another change is the widespread use of HDL synthesis for logic generation and simulators for logic simulation. These simulators do not replace the need to perform proper electrical engineering of spaceborne digital electronics, in particular signal and power integrity. |
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February 11, 2004 |
Overview Enclosed is the first summary report on the SX-S FPGA reliability for NASA space flight missions. This report provides a snapshot of the work accomplished to date, including the meeting held at NASA GSFC on January 7, 2004, a review of all available data and reports, and extensive analysis performed over the past month. A diverse team of 10 engineers from various NASA Centers and the Department of Defense was assembled for this task. The primary objective of this activity is to determine the root cause of failures of Actel SX-S devices, which are used extensively in NASA's spacecraft, both crewed and robotic, as well as to offer guidance to engineers testing and using these devices. This summary documents the findings and recommendations for the use of these devices in NASA and other mission- or safety-critical systems. A NASA Advisory will be submitted for dissemination, applications notes published, and seminars held to maximize the reliability of digital electronics systems. |
July 28, 2003 |
Summary If VCCI rises prior to VCCA and there are fast power cycles, large startup currents may be observed. This is a result of residual voltage on internal nodes, which bleeds off faster at high temperatures and slower at low temperatures. This update adds new data on the RT54SX72S. |
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Introduction Timing analysis for combinational and sequential circuits has always been a critical part of reliable hardware design. While historically a lengthy, manual process, the use of new Computer Aided Engineering (CAE) software tools and modern devices seemingly allows "push button" timing analyses with the gate array designer not seeing the intricate numerical details and calculations. The newest high-speed devices and the proper characterization of generic gate array devices present new challenges. |
Additional Information: pcn0304_inrush.pdf |
Summary It was recently observed that for a particular (listed below) power cycling sequence of VCCI and VCCA, a high ICCI inrush current was noted when the time between power cycles was short. |
Silicon Sculptor Software version 3.66 DOS and version 4.29 Windows and all RTSX-72S |
This is to inform Actel customers that Silicon Sculptor Software version 3.66 DOS and version 4.29 Windows and all RTSX-72S devices programmed with this software version are being recalled.
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Summary The RT54SX72A and RT54SX72S has, in addition to the three global clocks, 4 quadrant clocks. These clocks may accessed via specific I/O pins or from signals internal to the logic array. Although logically equivalent, the timing performance for distributing one signal to multiple quadrants differs significantly depending on the method used. The design software may allocate a signal to multiple quadrant drivers automatically, even if sufficient resources are available to locate all flip-flops in one quadrant. A discussion of this architectural feature and sample performance numbers are given below. |
qclk_e_reva.pdf (updated) |
Architectural Overview The A54SX72A and RT54SX72S devices offer four quadrant clock networks (QCLKA, B, C, and D) that can be driven from external points or from internal logic signals within the device at minimal die cost (Figure 1). Each of these clock networks individually drives a quadrant of the chip, or they can be grouped together to drive multiple quadrants.These additional four quadrant clocks are high-speed, low-skew networks dedicated to providing suitable paths for high-speed clocks. They can also be used for more local signals in need of low-skew paths or lines with high fanout such as reset and enable signals. Using these built-in networks enables better performance by reducing skew between loads and by freeing up regular routing resources that would otherwise be consumed by large buffer trees. Note: If a signal drives multiple quadrants, the amount of skew depends on whether the signal originates from outside of the device (e.g. QCLKBUF) or inside (e.g. QCLKINT). |
November 21, 2001 |
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SXA Tri-State Leakage |
Some limits have been changed to 20 microamps. |
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A summary of the IEEE JTAG TRST* pin configurations and terminations for members of the SX, SX-A, and SX-S families. Note that the revised data sheet for the RT54SX devices are incorrect; there is no pullup resistor for TRST* in the SX-series devices. |
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Summary Ground bounce, potentially large enough to cause an error in sensing logic level, was observed within an Actel 54SX32A. The magnitude of bounce was a function of output driver slew rate - faster outputs increased the effect. I/O power supply voltage also affected bounce with more observed in the 5V than the 3V parts. Temperature dependence of ground bounce was more complex. Bounce appeared independent of temperature for low slew outputs and increased when the part was cold for PCI type outputs. However, the data indicated that for the high slew outputs bounce decreased when cold. While simultaneously switched output (SSO) induced ground bounce was clearly observed, application functionality in many cases should not be compromised. Most designs have only a small number of potentially sensitive signals. Pin placement and driver slew selection can dramatically reduce bounce for those signals. An engineering peer review of preliminary pin assignments may be helpful in identifying these issues and developing solutions. In case of a problem discovered after pin assignments are frozen, changes within the FPGA such as adding internal delays to stagger outputs can lessen bounce. External filter components can also be used to reduce the impact of bounce. SSO induced ground bounce does occur but many design techniques can be applied to overcome this problem. |
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Abstract For the RT54SX72S, CQ208 package pin 13 is an I/O and is not a VCCI connection. The following versions of the data sheet, "RT54SX-S RadTolerant FPGAs for Space Applications" are incorrect:
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Abstract A simple circuit of one negative edge triggered flip-flop is shown below. This should increase the LET resistance of the memory element, when compared to an R-Cell in SX and SX-A technology. For SX-S, this is a technique that can be used to increase the number of flip-flops available. However, data indicates that an R-Cell was used, not the pair of C-Cells, which would give the user an implementation that did not have the expected SEU tolerance. |
| skew_notes.htm | |
| sx_sxa_jtag.pdf |
October 2002 |
hot_swap_cold_sparing_july_2002.pdf |
This note updated, July, 2002. "Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications," December 2001. |
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Introduction |
July 8, 2002 |
Issue Actel understands that customers may have difficulty meeting the 50ns Tr and Tf specification of the RT54SX devices for certain applications (see Note 1, Electrical Specifications). As reported by customers in their application of RT54SX programmed parts the maximum fall transition time specification could exceed the limits of the Actel data book for these parts (See Note 2 and 3 for other discussions on this). This may occur during a bus tri-state operation where there is no active pull up or pull down of the bus voltage and only a passive resistor of large value (~100 K .) to ground to discharge the bus. In this type of application, the only concern will be when the customer design has implemented an input or bi-directional user I/O function connected to the bus. The tri-state buffer implementation (output drive only) in an RT54SX device disables the input buffer and will not be a concern. With a corresponding large bus capacitance (~2700pF) the resulting fall times for input pins from the tri-stated bus operation on these or any similar Actel parts would be on the order of 500 µs, exceeding the specified 50ns maximum transition time. There may be concerns for functionality issues during the tri-state conditions as well as long-term reliability concerns. This report summarizes the findings of fall time experiments completed to determine any potential reliability issues with slow fall times. (July 10, 2002) Acrobat 4.0 or higher needed. |
June 14, 2002 |
Issue Actel understands that customers may have difficulty meeting the 10ns tR and tF specification of the RT54SX-S devices for certain applications. As reported by customers in their application of RT54SX-S programmed parts the maximum fall transition time specification could exceed the limits of the Actel data book for these parts. This may occur during a bus tri-state operation where there is no active pull up or pull down of the bus voltage and only a passive resistor of large value (~100 kohm) to ground to discharge the bus. In this type of application, the only concern will be when the customer design has implemented an input or bi-directional user I/O function connected to the bus. The tri-state buffer implementation in an RT54SX-S device disables the input buffer and will not be a concern. With a corresponding large bus capacitance (~2700pF) the resulting fall times for input pins from the tri-stated bus operation on these or any similar Actel parts would be on the order of 500 µs, exceeding the specified 10ns maximum transition time. There may be concerns for functionality issues during the tri-state conditions as well as long-term reliability concerns. This report summarizes the findings of fall time experiments completed to determine any potential reliability issues with slow fall times. (June 20, 2002). |
Tables: sx-a_sx-s_input_slew_rates.htm |
Introduction Actel’s SX-A and SX-S device families are designed to accommodate a variety of I/O standards. This allows users to easily integrate these FPGAs with other devices that have adopted a compatible I/O standard. In order to achieve this I/O flexibility as well as higher device performance, SX-A and SX-S devices use smaller device geometries. As a result, slow input signals with low slew rates, such as board power-on-resets or waveforms generated by a crystal oscillator, may be prone to functional failures in these devices. One approach for negating low slew-rate effects is the use of a Schmitt-trigger buffer applied at the input to the FPGA. This document discusses in detail the input slew-rate characteristics of the SX-A and SX-S devices and how the use of Schmitt triggers can aid in low slew-rate applications. Note: The application note suggests the use of HCxx logic driving RT54SX-S devices. At least some HCxx logic devices are not guaranteed to reliably drive RT54SX-S inputs with a 10 ns transition time requirement. (June 7, 2002) |
| silicon_explorer_terminations.htm | Signal Terminations for the Silicon Explorer (April 25, 2002) |
| SX-S_Output_Transients.htm | Some sample output transient data from an RT54SX72S, L/C T25KS001, S/N LAN6701. (11/29/2001) |
| SX-S_Clocks.htm | Clock Performance Parameters for the RT54SX32S and the RT54SX72S. (10/31/2001) |
| SX-S_Pin_Incompatibilites.htm | The RT54SX32-S and the RT54SX72-S are not 100% pin compatible. |
| SX_SX-A_Power_IO.htm | |
| SX-S_Input_Thresholds.htm | |
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Introduction One of the key benefits of Actel’s nonvolatile antifuse FPGA technology is the ability of the devices to be live at power-up. Since no configuration PROMs are required to download design information to the device, Actel FPGAs are ready to run as soon as the power-up sequence is complete. However, there are a few restrictions that need to be considered while designing with these devices. This Application Note explains all the requirements of Actel’s 54SX and RT54SX devices during power-up and power-down. In addition, this Application Note also discusses the behavior of outputs during power-up, explains when the device is functional, and provides recommended ramp rates for power-up. This report was measured in a laboratory environment. The values reported are typical values, and therefore, not guaranteed maximum or minimum values. (January 26, 2001) |
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Introduction Actel provides radiation tolerant FPGA devices for use in Aerospace applications. However, since the enhanced environmental properties of radiation tolerant devices are not required during prototyping, an inexpensive commercial device can be substituted during the design phase. With the introduction of the RT54SX-S family, customers can now use commercial design techniques and devices when designing and prototyping for this radiation tolerant family of devices. While the commercial devices are functionally equivalent to radiation tolerant devices, they differ architecturally and in their timing. |
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