NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

DRAFT

SX-S Input Thresholds

The RT54SX32S and RT54SX72S have logic input thresholds that are selectable on an individual I/O basis.  The levels are:

1. LVTTL
2. 3.3V PCI
3. 5V CMOS
4. 5V PCI/TTL

All inputs are 5 volt tolerant.  Note that the 5V CMOS input threshold, designed for increased noise immunity, is not available in the A54SX-A series, which are desirable for inexpensive prototyping.

Engineering evaluations of these inputs are now underway and the results of these evaluations will be included in this application note.  To date, the evaluations have focused on the new input level, 5V CMOS.

Measurements on a production RT54SX32S have shown a 5V CMOS logic threshold of ~2.8 V.  Test conditions were T = 25C, V_CCI = 5.0VDC, and V_CCA = 2.5VDC.  This was performed on an INBUF hard I/O macro.

Attempts to measure 5V CMOS logic thresholds on the clock buffers (CLKBUF, HCLKBUF) failed.   Following up with the manufacturer, it has been learned that the devices, because of the "hot-swap" I/O capability, can not have the 5V CMOS thresholds on the two different types of clock buffers.  For the HCLK, which is hardwired, there are no work-a-rounds.  The note below will show a work-a-round for the CLKBUF interface and a sample timing measurement.

Since the global clock network can be accessed from either a device pin (using CLKBUF) or any internal signal (using CLKINT) CMOS clock thresholds for the two global clocks can be achieved by bringing the clock signal into the chip via an INBUF macro and then routing it to a CLKINT macro.

A small test chip was designed to evaluate the impact of this work-a-round and analyzed with TIMER and Designer R1-2000.  Below is the evaluation circuit.

Circuit used for examining the timing delays when inserting an INBUF to
construct clock buffers with 5V CMOS compatible logic thresholds.

The design was imported into Designer R1-2000 and then placed and routed.   Two runs were made.  The first run was first hand-placed before routing; the second used fully automatic place and routing.  No major differences were observed.

The automatic placement software placed the INBUF macro close to the CLKINT macro which is critical for good performance.

Automatic placement of INBUF macro.   The INBUF macro is
configured with 5V CMOS compatible logic thresholds.

Timing Analysis Results

Worst-Case Conditions

Temperature   = 125C
Array Voltage = 2.3VDC
Speed Grade   = STD

TTL CLKBUF Buffer

Instance     Net        Macro    Delay      Total
ZQ0:D        Q0         OUTBUF    4.40 (r) 13.00
FF0:CLK      TTLCLK    DF1        1.70 (r)  8.60
XTTLCLK:PAD  XTTLCLK   CLKBUF    6.9  (r)  6.90

CMOS INBUF + CLKINT Macros

Instance     Net        Macro    Delay      Total
ZQ1:D        Q1         OUTBUF    4.40 (r) 12.70
FF1:CLK      CMOSCLK   DF1        2.10 (r)  8.30
CMOSCLK:A    CMOSCLKNQ CLKINT    4.60 (r)  6.20
XCMOSCLK:PAD XCMOSCLK  INBUF     1.6  (r)  1.60

Home - NASA Office of Logic Design
Last Revised: November 01, 2003
Digital Engineering Institute
Web Grunt: Richard Katz