NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

This chart is now obsolete as there are new data sheets but kept as a record.  Please use the updated version of this application note.

SX-S Clock Performance

Worst-case Military Conditions VCCA = 2.3V, VCCI = 3.0V, TJ =125 °C

Reference: SX-S Data Sheet, v0.2.

Parameter Description RT54SX32S-1 RT54SX32S RT54SX72S-1 RT54SX72S

Dedicated (Hard-wired) Array Clock Network
tHCKH Input Low to High
(Pad to R-Cell Input)		 3.4 4.0 5.8 1.8 (prob wrong)
tHCKL Input High to Low
(Pad to R-Cell Input)		 3.4 4.0 5.8 6.8
tHPWH Minimum pulse width HIGH 2.1 2.5 3.6 4.3
tHPWL Minimum pulse width LOW 2.1 2.5 3.6 4.3
tHCKSW Maximum skew 0.5 0.6 1.4 1.6
tHP Minimum Period 4.2 5.0 7.2 8.6
fHMAX Maximum Frequency 238 200 139 116

Routed Array Clock Networds
tRCKH Input Low to High
(Pad to R-Cell Input)		 Light Load 3.2 3.7 5.9 6.8
50% Load 4.0 4.7 7.4 8.7
100% Load 4.9 5.8 9.1 10.8
tRCKL Input High to Low
(Pad to R-Cell Input)		 Light Load 3.2 3.7 5.9 6.8
50% Load 3.8 4.4 7.0 8.2
100% Load 3.8 4.5 7.0 8.3
tRPWH Minimum pulse width HIGH 1.9 2.0 5.7 6.8
tRPWL Minimum pulse width LOW 1.9 2.0 5.7 6.8
tRCKSW Maximum Skew Light Load 1.9 2.0 3.5 3.7
50% Load 1.9 2.0 3.5 3.7
100% Load 1.9 2.0 3.5 3.7

 

Worst-case Military Conditions VCCA = 2.3V, VCCI = 4.5V, TJ =125 °C

RT54SX32S-1 RT54SX32S RT54SX72S-1 RT54SX72S

Dedicated (Hard-wired) Array Clock Network
tHCKH Input Low to High
(Pad to R-Cell Input)		 3.1 3.6 5.3 6.1
tHCKL Input High to Low
(Pad to R-Cell Input)		 3.1 3.6 5.3 6.1
tHPWH Minimum pulse width HIGH 2.1 2.5 3.6 4.3
tHPWL Minimum pulse width LOW 2.1 2.5 3.6 4.3
tHCKSW Maximum skew 0.5 0.6 1.4 1.6
tHP Minimum Period 4.2 5.0 7.2 8.6
fHMAX Maximum Frequency 238 200 139 116

Routed Array Clock Networds
tRCKH Input Low to High
(Pad to R-Cell Input)		 Light Load 3.1 3.6 5.7 6.6
50% Load 3.7 4.6 6.8 8.4
100% Load 4.9 5.8 9.1 10.8
tRCKL Input High to Low
(Pad to R-Cell Input)		 Light Load 3.1 3.6 5.7 6.6
50% Load 3.8 4.4 7.0 8.2
100% Load 3.8 4.5 7.0 8.3
tRPWH Minimum pulse width HIGH 3.1 3.7 5.7 6.8
tRPWL Minimum pulse width LOW 3.1 3.7 5.7 6.8
tRCKSW Maximum Skew Light Load 1.9 2.3 3.5 3.7
50% Load 1.9 2.3 3.5 3.7
100% Load 1.9 2.3 3.5 3.7

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Last Revised: December 05, 2003
Digital Engineering Institute
Web Grunt: Richard Katz
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