NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Act 3 Output Transients

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The Specification

ACT3

Normal operation for inputs and outputs will occur within 100 µs after V_CC reaches 2.75 V. Before reaching the point of normal operation, all inputs and outputs are in a high impedance state (tristate) regardless of V_CC rise time. I_CC rises to 10-60 mA when V_CC is between 2V and 3V and then returns to normal.

"A Power-On Reset (POR) Circuit for Actel Devices," FPGA Data Book and Design Guide, Actel Corp., 1995, pp. 3-81 to 3-82.

Some Sample Data

For a test circuit, an A14100A was used.  An OUTBUF was configured with the input to the macro tied to VCC - this case comes from a flight design!

Here are a few samples.   Note that there was a "memory effect" and that the results were not fully repeatable; there were some random variations.  So these are just a few samples and shows that the data of the application note must be done carefully.

     

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