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"Programmable Logic Application Notes"

EEE Links Index

Hi,

The following is an index of the "Programmable Logic Application Notes" column published in NASA's EEE Links.

July 2001

  1. We're Moving ...
  2. 2001 MAPLD International Conference
  3. Failure Reports On-Line
  4. Programmable Military Specifications Now On-Line
  5. Tutorials and Minicourses
  6. Loss of Control in PROMs
  7. Analysis Techniques: RSS Calculations of Digital Timing Delays
  8. Programmable Logic Device Failures
  9. SX32S and SX72S Pin Incompatibilities
  10. Termination of Unused I/O's in the RT54SX and RT54SXS Series Devices
  11. RT54SXS Series Devices: I/O Determinism During Power Transitions
  12. RT54SXS Series Devices: Input Thresholds
  13. SX-A and SX-S Series Devices: Power Sequencing Revisited
  14. RT54SXS Series Devices: Propagation Delay and Radiation
  15. Variables for Design Software: Placement and Routing
  16. Virtex FPGA: SEU Performance
  17. Minimizing HDL Design Errors

 

November 2000

  1. MAPLD International Conference
  2. SX and SX-A Series Devices Power Sequencing
  3. JTAG and SX/SX-A/SX-S Series Devices
  4. Analysis Techniques: Digital Timing Analysis Tools and Techniques
  5. Status of the Radiation Hard reconfigurable Field Programmable Fate Array Program
  6. Input Transition Times
  7. Apollo Guidance Computer Logic Study
  8. RT54SX32S Prototype Data Sets
  9. A54SX32A – 0.22 µm/UMC Test Results
  10. New FPGA Design Effort
  11. Ramtron FM1608 FRAM
  12. Analysis of VHDL Code and Synthesizer Output
  13. Startup Transients and Requirements
  14. Nonvolatile, Reprogrammable FPGA Data

 

May 2000

  1. 2000 MAPLD Conference
  2. Analysis Techniques: An Outline of Worst-Case Analysis Requirements for Digital Electronics
  3. Nonvolatile, Reprogrammable FPGA Data
  4. P&R and Propagation Delay
  5. In Situ Functional Testing
  6. SX-A Technology
  7. A42MX36 Heavy Ion Test
  8. National LVDS
  9. Long Term Anneal
  10. KPP- A VHDL Pre Processor
  11. Charge Pump Measurements
  12. QL3025/EPI Experimental Devices

 

August 1999

  1. 1999 MAPLD Conference
  2. 1999 IEEE NSREC and RADECS Oaoers
  3. Wide Field Infrared Explorer (WIRE)
  4. Low Voltage Dropout (LVDO) Regulators
  5. NASA Lessons Learned
  6. Is It Safe?

 

July 1998

  1. MAPLD
  2. NSREC ’98
  3. MAPLUG
  4. Proton Test Results from IUCF
  5. Summary of Proton Test on the Actel A1280A at Indiana University
  6. Summary of Proton Test on the Actel RH1020 at Indiana University
  7. Summary of Proton Test on the Actel CKJ911 Prototype at Indiana University
  8. Summary of Proton Test on the Actel RT54SX16 Prototype at Indiana University
  9. Summary of Proton Test on the Chip Express QYH530 at Indiana University
  10. Summary of Proton Test on the Quick Logic QL3025 at Indiana University
  11. Functional Failure of EEPROMs in the Heavy Ion Environment
  12. Act 1 SEU Summary
  13. Antifuse Hardness
  14. SEU Comparison of 1.0, 0.6, and 0.35 µm Hard-wired Flip-Flops
  15. Recent Act 2 and Act 3 Total Dose Results
  16. Recent Sub-micron Total Dose Results
  17. Miscellaneous

 

April 1998

  1. VDHL Coding Style in ACTmap
  2. Flip-Flops for the Radiation Environment
  3. Total Dose Qualification of the RH1020
  4. Antifuse Hardness Data
  5. Initial Evaluation of the Quick Logic pASIC 3 QL3025 Amorphous Silicon Antifuse FPGA
  6. RH1020 Single Event Upset Summary Report
  7. Continued Evaluation of the RT54SX16

 

January 1998

  1. New WWW Site For Programmable Logic and Devices
  2. Chip Express Update
  3. RADECS ’97 Paper
  4. Recent Test Results on PALs: Sypress BiCMOS 22V10C devices
  5. Detecting Asynchronous Loops with Designer
  6. Using Synopsis to Design Flip-Flops for the Radiation Environment
  7. Act 3 Technology at 125 MHz
  8. PGA to QFP Work-a-round for Designer
  9. Metastable States
  10. Upcoming Tests
  11. Recent TID Test Results
  12. In-Flight Experiment

 

September 1997

  1. Documenting DTAnalyze Results
  2. Recent ‘Programmables’ Paper: Radiation Effects on Current Field Programmable Technologies
  3. Other 1997 NSREC Papers of Interest
  4. RH1020 Testing
  5. RH1280 TID Capability
  6. Fast FPGAs
  7. Chip Express Update
  8. Follow-up Evaluation of Actel A3200DX Field Programmable Gate Arrays
  9. ACT 3 Update
  10. Preliminary Heavy Ion Evaluation of the Pico Systems Antifuse Programmable Substrate

 

June 1997

  1. Evaluation of the Chip Express QYH580 (LPGA)
  2. Preliminary Heavy Ion Evaluation of the Actel A32200DX Field Programmable Gate Array
  3. Field Programmable Gate Array (FPGA) Technology Prototype

 

March 1997

  1. Design and Programming Tips
  2. Single Point Failures
  3. Act 3 and C-Modules
  4. Adapters
  5. Floating Inputs
  6. Hardware Info
  7. More On A1020B Variants
  8. More Foundries
  9. More Act3 Developments
  10. Total Dose Results
  11. LPGA’s
  12. Programmables and Protons
  13. Pipeline Performance
  14. Design and Test
  15. Tying Inputs Together
  16. Chopper Circuit
  17. Digital Design Checklist
  18. Initialization
  19. State Machine Design
  20. Visibility
  21. Synchronization
  22. Redundancy
  23. Internal Oscillators
  24. Asynchronous Feedback
  25. Gates Clocks
  26. Summary of See Performance of Various FPGAs

 

November 1996

  1. Radiation-Hardened PALs
  2. Devices and Specifivation
  3. Process and Technology
  4. Packages
  5. Radiation Tolerance
  6. Design and Programming Tips
  7. Calculating Propagation Delays for Actel FPGAs
  8. Chip Edit Is Back
  9. Workstation Software
  10. ACTgen Tips
  11. Label It
  12. Fixing Pins
  13. Timing Analysis
  14. Viewlogic Save
  15. Design and Test
  16. Introduction
  17. ATE Capability
  18. Failure Types
  19. Fault Models
  20. Design Styles
  21. Hardware Info
  22. A1020B Variants
  23. More Foundries
  24. Act 3 Developments
  25. See Performance of FPGAs
  26. Programmables and Protons
  27. More on C-Module Flip-Flops
  28. Summary of See Performance of Various FPGAs
  29. Reprogramming
  30. Programming, Debugging, and Testing Tips
  31. Programming and S/W Updates
  32. Total Dose Performance at Low Dose Rates – Update

 

July 1996

  1. Design Tips
  2. Clock Skew
  3. Calculating Propagation Delays for Actel FPGAs
  4. Performance Comparison Between Various Families
  5. Pin Assignment Errata
  6. Unused Inputs
  7. High Level Design
  8. Presets and Clears
  9. Designer 3.0 Combiner
  10. See Performance of FPGAs
  11. Actels and Protons
  12. RH1280 and SEDR
  13. C-Module Flip-Flops
  14. Summary of See Performance of Various FPGAs
  15. Programming, Debugging, and Testing Tips
  16. Hot Socket
  17. Bug
  18. Handle With Care
  19. Verify All of the Special Purpose Pins
  20. Dynamic Burn-In
  21. Package Converters
  22. ESD and LIDS
  23. Total Dose Performance at Low Dose Rates
  24. Summary of Total Dose Performance

 

March 1996

  1. Actel/Loral FPGAs
  2. Devices
  3. Specification
  4. Foundry and Process
  5. Packages
  6. Timing Performance
  7. Programming
  8. Radiation Performance (RH1280)
  9. Design Tips (See Performance of Actel FPGAs)
  10. Programming Tips
  11. Socket Tips
  12. Act 3 Evaluation

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Last Revised: January 09, 2002
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