Programmable Logic Application Notes: September, 1997

Richard Katz Electronic Systems Branch
Goddard Space Flight Center
301-286-9705
richard.katz@gsfc.nasa.gov

This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter’s column will follow the format from the last edition; there will be a small section on some topics of interest and then several summary reports on programmable logic devices. Note that we’re including more graphs for total dose and single event effects. The report on the Chip Express Laser Programmable Gate Array expands on data in the last issue, providing a first look at the CX2001 series devices. Also, follow-up testing and analysis has been completed on the Actel A3200DX, with results on the 20,000 gate A32200DX and the 14,000 gate A32140DX. Next, more data is added to the Act 3 data base and the difference between MEC and Winbond foundries. Lastly, a first report on the Pico Systems antifuse-programmable substrate is given.

Documenting DTAnalyze Results (Win 95, NT) - In Designer, DTAnalyze is used in place of the older DOS Timer for static timing analysis. However, there is currently no ‘print’ or ‘save to file feature.’ To document your results, put the cursor over the desired DTAnalyze window and press ALT and PrintScreen; this saves the window graphics into a buffer. It can then be pasted into programs such as Word, WordPad, or Paint. It will not work with NotePad.

Recent ‘Programmables’ Paper - At the IEEE 1997 NSREC (Nuclear Space Radiation Effects Conference) we presented a talk on programmables: Radiation Effects on Current Field Programmable Technologies by R. Katz, JJ Wang, B. Cronquist, R. Koga, S. Penzin, and G. Swift. The talk summarized and analyzed radiation effects on the most current devices and early preproduction prototypes, including programmable substrates. Included in the talk was results on amorphous silicon antifuse heavy ion radiation tolerance. http://flick.gsfc.nasa.gov/radhome/papers/slideshow/index.htm is now available. The paper based on the presentation has been accepted for publication in the December 1997 Issue of the IEEE Transactions on Nuclear Science; pre-prints should be available by October 1.

Other 1997 NSREC Papers of Interest - Ionizing Radiation Response of an Amorphous Silicon Based Antifuse by J. Benedetto and C. Hafer of UTMC; Single Event Gate Rupture in Thin Gate Oxides by F. Sexton, et. al. of Sandia National Laboratories; Single Event Upset in Flash Memories by H. Schwartz, D. Nichols, and A. Johnston of JPL; and SEU Hardening Approaches in Spaceborne Applications Using COTS by G. Lum, Lockheed Martin Missiles and Space.

RH1020 Testing - The RH1020 has been tested for latchup and fuse damage from heavy ions. The RH1020 is based on the A1020B design, which is susceptible to latchup at moderate LETs. However, the RH1020 is fabricated on 5 um epi on a radiation-hardened line versus the 10 um epi at a commercial foundry and no latchup was detected. Another difference between the RH1020 and the A1020B is antifuse thickness, with the antifuse being increased to about 96 Å from the nominal 86 Å. Heavy ion testing showed a significant increase in antifuse hardness. Heavy ion SEU testing is scheduled for the week of September 22. Power measurements on our SEU DUTS show that the RH1020 consumes slightly less power than the commercial A1020B. Here are the measurements at V_CC = 5VDC, 25ºC, F=500 kHz, with all currents in mA:

MODE	RH1020	A1020B
STATIC	0.98	1.00
CLOCK	7.80	8.05
DYNAMIC	30.70	31.65

RH1280 TID Capability - The RH1280 has been tested for total ionizing dose capability to greater than 2 Mrad (Si). Details will be reported in the next edition.

FAST FPGAs - Preparations are being made to evaluate the DynaChip DL5000 family of fast Field Programmable Gate Arrays. These SRAM-based reprogrammable BiCMOS devices feature: up to 10,000 gates, complex operations up to 200 MHz, ECL, PECL and GTL interfaces (and companion chips for TTL-level interfacing), 6 low-skew clock trees (2 global, 4 quadrant), predictable, short routing delays based on their ‘active repeaters’ in the routing array and JTAG Boundary Scan. The 5,000 gate DL5256 has 256 logic blocks in a tiled architecture. The logic blocks are coarse and contain 2 flip-flops while having 18 inputs (1 clock, 1 set/reset) and 3 outputs, 1 registered and two combinational. Functions are implemented by gates and not lookup tables as found in Xilinx devices.

Some additional radiation testing has been completed on the QYH500 series of FPGA’s, filling in some spots on the X-section vs. LET curve for both 5.0 and 3.3 volts. The QYH500 device previously described was implemented in the QYH530, not the QYH580 reported. Both the QYH500 and the CX2001 devices described here are currently being fabricated using the One-Mask technology. These die will be used for further radiation evaluations, a destructive physical analysis (DPA) and incorporation into our flight technology experiment, where the devices will be instrumented primarily for SEU’s. Current will also be monitored as will functional performance. Along with packaged devices, an effort is ongoing to package both CX2001 and QYH500 die into the Pico Systems antifuse programmable substrate; if completed on time, this MCM will be flown as part of the experiment. Additional prototype devices have been received and an SEE evaluation will be performed in Sept., 1997. Additional TID tests at both VCC=3.3 and 5.0 volts will be performed in October, 1997.

The CX2041 is a member of the Chip Express CX2001 family. This family is a 0.6 m m three layer metal epi-CMOS technology. The CX2001 gate array family can be configured to yield greater than 100,000 usable "gate array gates" plus up to 96 kbits of embedded SRAM.

This technology utilizes two types of cells: I/O cells and logic modules. The I/O cells may be programmed into a variety of configurations; however, there is no storage available in these cells. I/O cells are PCI compliant and support 5.0 VDC, 3.3 VDC, and mixed-voltage board designs or can be configured as power and ground pins. The logic modules are coarser than that found on the QYH500 series described previously (2-input NAND gates) and is multiplexor-based, ironically similar in concept to the Act 1 module. The CX2001’s module consists of a 2:1 multiplexor fed by a 2-input AND gate on one leg and a 2:1 multiplexor on the other. The select function is generated by an additional 2:1 multiplexor. Maximum flip-flop toggle rate is specified at 800 MHz. Power dissipation is 1 m watt/MHz/gate @ 3 volts and 2.5 m watt/MHz/gate @ 5 volts. Like the QYH500 series, these devices can be programmed with a laser for prototyping (LPGA) or by a single mask etch (One-Mask). The LPGA devices are non-passivated.

Additional features include a PLL with a maximum frequency of 250 MHz. For testability, the CX technology library, for each flip-flop, has a matching scan macro, which is identical in both speed and area to the original macro, resulting in no overhead for scan insertion. The ASIC core may be run at either 3.3 or 5.0 volts providing flexibility for either lower power or higher speed.

For this evaluation, the CX2041 was configured to be pin compatible with an Actel A1280A in a CPGA176 package for both a proof of concept and compatibility with existing test infrastucture. Chip Express is foundryless; the CX2041 series of devices is fabricated by Tower. While the CX2041 has SRAM cells, they were not used for this first-look test. The design of a test chip with SRAM (for SEU testing) is in progress.

TID testing was performed on a sample CX2041 (LPGA) at NASA/GSFC using a Co-60 source. The device was statically biased at V_CC = 5.0 VDC with all inputs terminated to ground. The dose rate was 5 krads (Si) / day. Three device current parameters were measured: standby (the entire chip static), clock on (measuring the clock distribution network), and dynamic, with all elements toggling at approximately 500 kHz.

Testing proceeded until 14 krads (Si). No functional failures were detected and a plot of I_CC vs. radiation and annealing is given below. All annealing was biased at V_CC = 5.0VDC and was at room temperature.

The identical data is presented on two scales to show both the performance of the device over the 14 krad (Si) exposure and its behavior at lower doses where the supply currents are more reasonable. The "steps" between 1 and 2 mA in the high resolution plot, for example, are an artifact of the power supply (HP6624A) used for current monitoring and is digitization noise.

As can be seen from the graph, the device gave a good response until approximately 7 to 8 krads (Si), when the supply current started to rapidly increase. A functional test was performed on the sample approximately 17 hours after being removed from both the radiation chamber and bias. The device passed functional tests and device currents did decrease. Here’s a summary:

The device has passed continuous functional tests with no errors and the currents continue to decrease. At present, the static I_CC current is below 18 mA.

The previous edition of EEE Links reported on the initial heavy ion testing of the A32200DX and the fact that the device had latched up. This section will describe follow up tests and analysis.

The A32140DX is part of the Actel Integrator Series of FPGAs that consists of the A1200XL products as well as the A3200DX products. The A1200XL devices are derived from and share a user architecture with the more familiar A1200A series parts, such as the A1280A which has been heavily tested by NASA and the aerospace industry. The A3200DX family shares the same C-Module and S-Module ‘logic diagram’ with the A1200 series; the I/O-Module structures are also similar but differ with the addition of JTAG 1149.1 capability in some A3200DX products.

The A3200DX family introduces new architectural features. These include larger capacity (higher gates available, wide fan-in decode modules, dual-port SRAM, higher I/O counts, IEEE JTAG 1149.1 support, and 4 low-skew quadrant clocks.

The DUT design used for the A32140DX evaluation is called the TD32140 and was originally intended for total dose testing of the A32200DX device; however, since the 20,000 gate A32200DX latched during heavy ion testing, the A32140DX 14,000 gate device was substituted for total dose testing. This device includes the usual test structures such as flip-flops, gates, counters, shift registers, etc. This design pattern had the JTAG feature disabled.

The test set consisted of a custom test fixture which provided the ability to start/stop clocks, reset the device, test all functions, provide monitors and output error pulses. For this TID test, the device remained under static bias. A strip chart is made of I_CC vs. dose while the device is irradiated. The dose rate used for this test was 0.5 krads (Si) / Hour. One device was tested.

This device failed at approximately 2.2 krads (Si). At that point, the current suddenly increased and tripped the protection on the power supply, ending the test. The current strip chart is shown in the figure.

The initial suspect for the cause of latchup was the SRAM modules; this is the key new technology that is in the A3200DX family. An examination of the SRAM circuit layout did show that there were no guard

rings. Physical analysis of the failed samples showed that the process did include an epi-layer with correct thicknesses (i.e., 8.5 and 9.0 m m). Additional heavy ion tests were conducted with new A32200DX devices and A32140DX’s. In both devices, the JTAG feature was disabled. As shown in the graph below, there was no indication of latchup in the A32140DX. A rough x-section vs. LET graph for the A32200DX is shown below.

Act 3 devices such as the A1460A and the A14100A are being used. Total dose testing to date shows that the MEC devices are radiation-tolerant with respect to total dose. Winbond devices have done poorly and no Chartered Act 3 devices have been tested yet. The figure below shows a comparison between MEC and Winbond devices which appears to be typical. Flight parts from the EO-1 A14100A (MEC) lot are currently being irradiated and will be reported on in the next issue.

PRELIMINARY HEAVY ION EVALUATION OF THE PICO SYSTEMS ANTIFUSE PROGRAMMABLE SUBSTRATE

The Pico Systems antifuse programmable substrate functions as a Programmable Silicon Circuit Board (PSCB), providing a quick turnaround custom MCM substrate technology. To create a unique MCM substrate, "generic" substrates are taken from an existing supply of pre-fabricated but unprogrammed wafers and a connection pattern is electronically programmed in, configuring the wafer to implement the specified routing structure. This is analogous, in principle, to the role of routing structures in antifuse-based FPGAs.

The device is a 4-layer Aluminum (Al) metallization system on a Silicon (Si) substrate; M1 and M2 are power and ground planes and are accessed through vias. M3 and M4 are signal interconnect layers accessed through a sea-of-antifuse architecture. The top layer of substrate has a near sea-of-bond pads to allow connections to the signal lines and power/ground connections. The substrates are processed using standard semiconductor Si processing techniques with 15 m m line width and a 25 m m pitch. Within the substrate, the minimum dimension is 2 m m x 2 m m at a programmed antifuse junction. The substrates are completely passive.

The antifuses are electronically programmed. Using a 20 mA current, the initial resistance distribution is bimodal with 200 O typical and some at ~ 1 k O . A subsequent programming pulse of 400 mA reduces the antifuse resistance to 1 O . Programming at higher currents eliminates the bimodal distribution.

Previous radiation testing have characterized the substrates to 1 megarad (Si) with no failures. Additionally, NASA/GSFC has conducted antifuse reliability/stress tests with no failures [Harry Shaw].

The DUT consisted of four quadrants; two of these consisted of an array of unprogrammed antifuses configured by crossing X and Y layers of signal interconnect. These lines, in their respective groups, result in a two-terminal device where there were ~500 ‘biased’ antifuses per group. The bias for each of these two quadrants was controlled by a section of a HP6629A System Power Supply, configured with a current limit of 20 mA. A 0.3 m F capacitor was used in parallel for ESD protection.

The other two quadrants were configured in a series arrangement of 5 programmed antifuses each; the HP6629A was configured in constant current mode to provide a constant bias current of 10 mA and 20 mA for the two strings. Because of time limitations, only the first of the two strings was wired and powered for the test. Preliminary analysis of these strings on our 3 DUTs showed no ill effects during heavy ion irradiation and will not be discussed further in this report.

The test board consisted of three DUTs and was configured to test one DUT at a time. Additionally, because of the available beam diameter, approximately 50% of each DUT were irradiated for each run. A PC monitored the current and voltage for each of the three channels (two antifuse arrays, one serial string) and recorded the measurements. Current resolution for the monitor was 10 m A.

All exposures were done at normal incidence; based on dielectric antifuse testing it was felt that this would most likely be the worst-case; the next heavy ion exposure will test this assumption. The test was designed for two voltage ranges: 5V and 7V for digital applications; 12V and 15V for analog applications.

The initial ion used was 345 MeV Iodine with a LET of 60 MeV-cm²/mg and a range of 32.8 m m. Later, 290 MeV Bromine was used with a LET of 37 MeV-cm²/mg and a range of 37.3 m m. Discussions with the vendor confirmed that this range was sufficient to pass through the antifuse. For each run, a nominal fluence of 1 x 10⁷ ions/cm² was used unless a failure was observed. The test was to establish that the device was good and an initial ion of Iodine was selected for this purpose.

The devices were to be tested first for digital applications (5V nominal followed by 7V for worst-case margin), and then for analog applications (12 maximum rating of the device followed by 15V for margin) and then finally the voltage would be raised until there was a failure. The failure could be either by heavy ion damage or, if the voltage was raised high enough the power supply will programming the antifuse; additionally, this would establish that the DUT was in the correct state for the test and was not damaged during handling, etc.

With the Iodine ion, S/N 001 substrate passed initial ‘digital’ tests at both 5V and 7V. During the 12V irradiation, one side failed and the power supply went into a constant current mode supplying the full 20 mA. The device was power cycled and the fault remained; 20 mA of current was again measured. An examination of the current strip chart showed a sudden jump in the current and not a slow, continuous rise. This sudden jump was characteristic of all failures. The failure point was repeated on the other side of the array giving a second consistent data point. For all failures during this test, each failure point was duplicated in a similar manner and the results were 100% consistent.

The next step was to determine, for the Iodine ion, what the voltage threshold for damage was. Since there was no experience in this type of testing for this device and run times are relatively expensive; a 1-volt step size for the bias was used.

S/N 002 was initially tested at 7V and passed. At 8V the device failed immediately. For S/N 003, the ion was changed to Bromine. Again, the testing started at 7V and the voltage was increased in 1V increments. Both sides failed at 11V.

The first will be a characterization and analysis of the failures observed to date. Laboratory analysis of failed site is underway. Liquid crystal analysis was useful in identifying failure sites. Further data and analysis will be presented in the next issue.

The second will be additional heavy ion exposures with lower LET ions to further characterize the failure threshold voltage. Additionally, we will attempt to measure failure cross-sections, which are difficult, since each failure destroys the device. Lastly, limited angle testing will be performed to verify the assumption that normal incidence is the worst-case. Additional heavy ion test was performed in July 1997 and the data is still being analyzed. However, it was clear that normal incidence was the worst-case for antifuse failure, as expected, similar to ONO antifuse testing.

Additionally, making the devices more resistant to heavy ion upset is being explored; these initial test devices were developed and screened for commercial applications. Areas of investigation includes screening substrates for higher programming threshold voltages and tighter distributions as well as raising the programming threshold voltage; the current value of approximately 30 V is not a limitation of the technology. Some testing was performed in July, 1997. While in some cases improvements were seen, a quantitative assessment is currently being made.

	Pre-Rad	Post 14 krad (Si)
static	0	110.0
clock network	4.7	114.3
dynamic	12.7	123.4

Ion	LET	Threshold	Electric Field Strength	% of Prog. Voltage
	MeV-cm^2/mg	(Volts)	(Volts/cm)
Br	37	10.0	2.00E+05	0.33
I	59	7.0	1.40E+05	0.23

PROGRAMMABLE TECHNOLOGIES WEB SITE

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Programmable Logic Application Notes

from NASA's EEE Links

PROGRAMMABLE TECHNOLOGIES WEB SITE

A scientific study of the problems of digital engineering for space flight systems, with a view to their practical solution.

Programmable Logic Application Notes

from NASA's EEE Links

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.