This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter’s column will differ from previous editions; there will be a small section on some topics of interest and then two summary reports on programmable logic devices. The report on the Chip Express Laser Programmable Gate Array expands on data in the last issue. Also, preliminary testing has been completed on the Actel A32200DX, a 20,000 gate FPGA; the A32140DX device with 14,000 gates will be tested in July My apologies for not being able to complete the usual article in time to meet the deadline; please give me a call or e-mail if additional information is needed. The topics of interest will be expanded on in the next edition of EEE Links.
Topics of Interest
Acknowledgements and References
NASA/GSFC - Ken LaBel (http://radhome.gsfc.nasa.gov)
Actel Corp.: JJ Wang
Gary M. Swift : California Institute of Technology/Jet Propulsion Laboratory
Martha O’Bryan, Hughes STX
EVALUATION OF THE CHIP EXPRESS QYH580 (LPGA)
Test Date: February, 1997, March, 1997, May, 1997
Test Location:
Brookhaven National Laboratory (Heavy Ion)
NASA/GSFC (Total Dose)
NASA/GSFC (DPA)
Test Device: Chip Express QYH580
Prepared By: NASA/GSFC
INTRODUCTIONThe QYH580 is a member of the Chip Express QYH500 family. This family is a 0.8 m m bulk CMOS technology. The QYH500 gate array can be configured to yield up to 60,000 usable "gate array gates". This technology utilizes two types of cells: I/O cells and 2 input NAND gates. The I/O cells may be programmed into a variety of configurations; however, there is no storage available in these cells. The two input NAND gates can be configured to provide buffers, logic functions, or flip-flops. The I/O structure is flexible and the devices may have the pins configured per user specifications. For this evaluation, the QYH580 was configured to be pin compatible with an Actel A1280A in a CPGA176 package for both a proof of concept and compatibility with existing test infrastructure. Chip Express is foundryless; the QYH500 series of devices is fabricated by Yamaha.
The QYH500 series is a channeled gate array architecture. Metal routing segments are "pre-placed" in the channels and all possible connections are made during integrated circuit fabrication. The chip is "programmed" by selectively opening connections leaving the interconnect in a state which implements the design netlist. This is opposite of antifuse-based Field Programmable Gate Array (FPGA) technology where connections are made during programming by making an antifuse into a conductor. Note that only a small fraction of possible connections are needed in a gate array; thus in an FPGA a small number of connections must be programmed and in the QYH500 the majority of connections must be made into open circuits.
The QYH500 series, for the purposes of this evaluation, can be programmed using two different techniques for the identical base arrays. The first technique utilizes a laser to remove the unwanted connections and takes on the order of 1 hour at the factory. Turn around for these Laser Programmable Gate Arrays (LPGA) is on the order of days. A one mask technology can remove metal connections from the base array on two levels of metal using a single masking step. In both cases, unused routing segments are left floating. For quick prototypes (as were our test devices) the LPGA is used and the device is not passivated. The 883-qualified devices are processed using one mask technology and are passivated following processing. The devices are qualified for both VCC = 3.3 and 5.0 volts.
This evaluation is considered preliminary: 3 devices were used for heavy ion testing, 1 for total ionizing dose (TID) testing, and several unprogrammed devices were used for a quick, coarse, destructive physical analysis. The sample device utilized approximately 35,000 gate array gates, roughly 4 times that of our A1280A 1.0 m m samples. It was observed even with the higher gate counts, the dynamic power of the QYH500 was less than the A1280A; static power was essentially 0 uA (our system, as configured, had a measurement resolution of 10 m A).
The CX2000 series of devices is a 0.6 m m epi-layer technology fabricated by Tower Semiconductor. This part will be evaluated in future tests (July, 1997).
TOTAL IONIZING DOSE TEST
TID testing was performed at NASA/GSFC using a Co-60 source. The device was statically biased at VCC = 5.0 VDC with all inputs terminated to ground. The dose rate was 5 krads (Si) / day or 0.058 rads (Si) per second. Functional tests were run at each radiation step of 5 krads (Si) and three device current parameters were measured: standby (the entire chip static), clock on (measuring the clock distribution network), and dynamic, with all elements toggling at approximately 500 kHz.
No functional failures were detected and a plot of ICC vs. radiation and annealing is given below. Testing proceeded to 20 krads (Si). All annealing was biased at VCC = 5.0VDC and was at room temperature.
HEAVY ION TESTING
Heavy ion Single Events Effects (SEE) testing was performed at Brookhaven National Laboratory. The device was monitored for single event upset (SEU), single event latchup (SEL) and device functionality. Strip charts were made of ICC vs. time. Nominal fluence for each run was either 0.5 x 107 or 1x107 ions/cm2. Runs were performed with VCC either in the standard 5.0 VDC ± 10% range or in the 3.3 VDC ± 10% range.
No functional failures were observed during testing. Latchup was detected at relatively high LETs with VCC in the 5.0 VDC ± 10% range; no latchup was observed in the lower voltage range up to an LET of 74 MeV-cm2/mg. Latchup data is summarized in the chart below. SEU performance was very good with upsets first detected near LET = 40 MeV-mg/cm2 with a very small cross-section; the SEU performance is also summarized in a chart below. SEU performance has been measured for both 5.0 and 3.3 volt bias levels. The good SEU performance is believed to come from the relatively high capacitance of the "pre-laid" metal routing segments. Note that this performance is similar to that observed for Actel C-Module flip-flops in one of it’s two storage states which uses a similar routing segment scheme.
Points on the graphs at the 1x10-10 line indicate that no SEE was detected for that run.
DESTRUCTIVE PHYSICAL ANALYSIS
Unprogrammed devices from the QYH500 and CX2000 series were subject to a quick, rough, destructive physical analysis. No obvious defects were noted and the preliminary evaluation showed processing consistent with 883 standards. Fully processed samples are expected for a more thorough analysis in the near future.
The CX2000 series has a very high I/O pin count. Note, in the photograph below, that many of the I/O pads are staggered. This can have implications for package selection and chip on board (COB) or multi-chip modules (MCMs).
File: 103x2200.bmp
Software and Design Flow
Chip Express has two families for low volume applications using it's LPGA and OneMask technologies; the QYH500 is 0.8 micron, two level metal and the CX2000 family is 0.6 micron, three level metal. The "golden" simulator for both parts is Cadence Verilog XL. Also supported for signoff are Synopsys VSS and Model Tech's V-System with the VHDL flow utilizing Vital-95. Synthesis for these devices is provided by Synopsys' Design Compiler and Exemplar Leonardo. Scan insertion is accomplished using either Synopsys' Test Compiler or Syntest's Picasso. Motive is used for static timing analysis.
For the QYH500 family only, Viewlogic schematic capture and simulation (ViewDraw and ViewSim) are supported.
PRELIMINARY HEAVY ION EVALUATION OF THE ACTEL A32200DX FIELD PROGRAMMABLE GATE ARRAY
Test Date: May, 1997
Test Location: Brookhaven National Laboratory
Test Device: A32200DX, TD32200 Pattern
Foundry: Chartered
Lot Codes: ACQ03818.1/456157, ACQ06719.1/497634
Prepared By: NASA/GSFC (R. Katz, A. Feizi), Actel Corp. (J.J. Wang)
INTRODUCTION
The A32200DX is part of the Actel Integrator Series of FPGAs that consists of the A1200XL products as well as the A3200DX products. The A1200XL devices are derived from and share a user architecture with the more familiar A1200A series parts, such as the A1280A which has been heavily tested by NASA and the aerospace industry. The A3200DX family shares the same C-Module and S-Module ‘logic diagram’ with the A1200 series; the I/O-Module structures are also similar but differ with the addition of JTAG 1149.1 capability in some A3200DX products.The A3200DX family introduces new architectural features. These include larger capacity (higher gates available, wide fan-in decode modules, dual-port SRAM, higher I/O counts, IEEE JTAG 1149.1 support, and 4 low-skew quadrant clocks.
The A32200DX has the following capabilities:
DUT and TEST DESIGN
The DUT design used for this evaluation is called the TD32200 and was originally intended for total dose testing of this device. It includes the usual test structures such as flip-flops, gates, counters, shift registers, etc. Additionally, it utilizes the quadrant clocks and the SRAM bits. The design has a built-in-test (BIT) capability for the SRAM where different patterns are successively written to and read back/checked from the SRAM. Internal monitors are available showing that the BIT is running and error pulses are output whenever a SRAM error is detected. This design pattern had the JTAG feature enabled.
The test set consisted of a custom test fixture which provided the ability to start/stop clocks, reset the device, test all functions, provide monitors and output error pulses. During a SEE run, the error monitor is run into a counter; after a test run, the entire functionality of the DUT is verified. Additionally, strip charts are made of ICC vs. time.
For this test, the DUT is packaged in a PQFP208 package. The device has a 10 µm epi-layer, common to all Actel commercial and military devices. These samples, from two different date codes, were manufactured at the Chartered foundry.
TEST RESULTS SUMMARY
Initial exposures used 290 MeV Bromine, with an LET of 37 MeV-cm2/mg and a range of 37.3 m m with normal incidence. All 4 runs with S/N 001 appeared to latch with high currents. The average latchup cross section was > 3.7x10-5 cm2. S/N 002 behaved similarly. A sample strip chart of ICC vs. time is shown below. S/N 001 was also exposed to 265 MeV Nickel, with a LET of 27 MeV-cm2/mg and a range of 42.2 m m with normal incidence. The device quickly latched.
A32200DX Latchup Current Strip Chart
ANALYSIS AND FUTURE WORK
The initial suspect for the cause of latchup was the SRAM modules; this is the key new technology that is in the A3200DX family. Previous SEE testing on the A1200XL series (both 0.6 and 0.8 m m) showed no sign of latchup. An examination of the SRAM circuit layout did show that there were no guard rings. The next round of tests will include the same TD32200 pattern with the JTAG circuitry disabled and a similarly configured A32140DX; this device does not have the SRAM modules. Lastly, the failed DUTs have been sent to failure analysis for verification of epi-layer thickness.
FIELD PROGRAMMABLE
GATE ARRAY (FPGA) TECHNOLOGY PROTOTYPE
Test Location: Brookhaven National Laboratory (Heavy Ion), Indiana University (Proton), NASA/GSFC Bldg. 22 (Total Dose)
Test Device: MKJ911, KJ911
Prepared By: NASA/GSFC (R. Katz)
INTRODUCTION
The MKJ911 and the KJ911 devices represent technology prototype Field Programmable Gate Arrays. While similar in respect to previous antifuse-based devices on the market, they have significant new technologies and architectural features; these are applicable both to commercial and space-borne applications. This report will review some of these key technologies, their relevance to space-based applications, and a preliminary radiation evaluation. Certain details such as gate count capability are omitted, as they are considered by the manufacturer to be competition sensitive and do not affect this study. The MKJ911 and the KJ911 are internal code names for these technology prototypes.
Most FPGA’s have used a channeled gate array architecture; that is, routing resources were located mainly in the channels in between rows of logic modules. For SRAM-based FPGAs, this is necessary since the memory elements and pass transistors need a substrate for the fabrication of transistors. These, combined with the routing segments, account for ~ 50% of the area of an FPGA. For the Actel dielectric antifuse (ONO – oxide nitride oxide), a channeled architecture was also used; the antifuses use the substrate for one terminal and polysilicon for the other. While in principle the antifuse can be fabricated between two layers of polysilicon, it is not practical to do this. Additionally, certain pass transistors need to be fabricated for testability and programming structures. Typical resistances of the dielectric antifuse are between 300 and 500 ohms. First generation Quicklogic devices also used a channeled architecture with the metal-to-metal antifuse.
Two key technologies, among others, permit an improvement in FPGAs: three layer metal processes and the metal to metal antifuse. These two technologies permit antifuses to be fabricated ‘on top’ of the logic modules, drastically cutting the size of the die and making parasitic capacitances less, improving speed. Additionally, the metal to metal antifuse has a typical resistance of 25-50 ohms and a lower capacitance than dielectric antifuses, also improving routing speed. On the negative side, the metal to metal antifuses have higher leakage currents than their dielectric antifuse cousins.
An additional benefit of the metal to metal antifuse is its lower programming voltage (for FPGAs and PALs); this is typically 10-11 volts as compared to the 18-20 volts for dielectric antifuse products. This makes the construction of high voltage transistors simpler and permits the use of thinner epi-layers. The high voltage of the Actel RH1280, for instance, limited the epi-thickness to 5 m m; the KJ911 has been fabricated with 2 m m epi.
Additionally, the MKJ911 and the KJ911 have significant architectural improvements over previous generation metal-to-metal antifuse products and dielectric antifuse devices; these are not discussed here, as the information is not yet released.
DUT and TEST DESIGN
Two different DUTs are used; both are identical FPGA designs and have identical patterns. The pattern used is called BURN, which was designed for testing of the silicon technology. The MKJ911 device is fabricated at Matsushita and has a 10 m m epi-layer; the KJ911 is fabricated on Lockheed-Martin’s radiation-hardened line and uses a 2 m m epi-layer. All devices are in a PQFP208 package.
The test of the device uses the ‘emulated gold chip’ approach. An Actel A1020 has device stimulation capability, error detect capability, built-in-test (BIT), and a gold chip emulation of the (M)KJ911. If an error is detected, it is classified as one of three types, depending on the chip section and state, and error pulses are put out on one of three corresponding lines. In the event of an error, the A1020B will reset both the DUT and the emulated DUT and they will resume operation in lock step. The structure of this design (BURN), which consists of structures designed to check IC reliability, results in an error count that is biased slightly high; the cross-sections reported here should be considered an upper bound.
In addition to monitoring for SEU’s, the power supplies’ currents are monitored. These devices use a 3.3 VDC supply for the logic core and are capable of mixed voltage I/O. For these evaluations the I/O modules were configured in 3.3 volt, 5 volt-tolerant mode.
Lastly, the as tested configuration had the IEEE JTAG 1149.1 port enabled; the optional hard reset for the TAP controller is not implemented on these prototypes.
The identical test configuration is used for heavy ion, proton, and total dose testing. All DUT card I/O is buffered with RS-422 drivers and receivers. For total dose testing, the support IC’s are shielded and the DUT is configured with a static bias.
The DUT and the support IC’s and are located on independent power supplies.
TEST RESULTS SUMMARY
Three types of tests were run: heavy ion, proton, and total ionizing dose.
Both of the device types, MKJ911 and KJ911 were tested for heavy ion SEU susceptibility. They both showed a similar upset threshold; the lowest LET where upsets were detected was 18.8 MeV-cm2/mg for the 2 m m epi KJ911 and 13.2 MeV-cm2/mg for the 10 m m epi MKJ911. Additionally, both devices appeared mildly susceptible to upsets that resulted in a loss of functionality and a change in supply current (both up and down). It is suspected that these were upsets in the JTAG TAP controller. The SEU results are summarized below. Note that for these samples, the 2 m m epi-layer parts had a smaller cross-section than the 10 m m epi-layer devices, for equal supply voltages.
The MKJ911 was tested at the Indiana University cyclotron with 196 MeV protons. No upsets were detected. An ICC vs. dose strip chart is included on the following page. This commercial device (MEC foundry) showed good total dose performance; after 50 krads (Si) exposure in a short period of time, the supply current increase was still relatively moderate. Part-to-part and lot-to-lot variance in total dose performance for this commercial foundry has not yet been determined.
Lastly, devices are being total dose tested in the NASA/GSFC Cobalt-60 cell. To date, a device from the Lockheed-Martin foundry has accumulated 200 krads (Si) at a dose rate of 2 krads (Si) per hour; no degradation of the device has been observed (i.e., no changes in the device supply currents, static and dynamic) and the device passed functional testing.
CONCLUSION AND FUTURE WORK
Further work is planned for the (M)KJ911 series. This includes heavy ion tests with higher LET ions, additional proton tests, and a more in-depth TID study. Additionally, leakage current performance as a function of temperature will be investigated. Prior to the completion of these tests, a new test pattern will be put into the (M)KJ911 series, designed specifically for radiation, performance, and reliability evaluations.
The MKJ911 has the potential to make a high-speed radiation-tolerant FPGA. The SEU threshold of approximately 13 MeV-cm2/mg at VCC = 3.0 volts is ‘moderate’ but far superior to the performance of S-Module flip-flops in other Actel devices running at higher supply voltages, which is the current base line for many missions. For the high speed applications this device is designed for, the 3.3 VDC core voltage will be critical for maintaining reasonable power dissipation levels. The device has shown immunity to proton upset with 196 MeV protons, a problem with the A1280XL series devices (including the RH1280) and the 0.8 m m Act 3 family (A1460A, A14100A), for example.
The KJ911 improves upon the performance of the MKJ911; this is believed to be primarily the result of the processing at the Lockheed-Martin facility. The use of the 2 m m epi-layer may contribute to the lower SEU cross-section and higher upset threshold of the KJ911 as compared to the MKJ911; however, for SEU performance, the device is still considered radiation-tolerant. Total dose capability, however, is in the radiation-hardened class. Currently, the KJ911 is the overall hardest FPGA of any that we have tested to date.
The KJ911’s sea of gates architecture results in a decreased die size relative to a channeled gate array architecture. This, combined with the circuit design internal to the KJ911, should make the device amenable to SEU-hardening while maintaining a relatively small die size and good electrical performance.
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