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A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

PROGRAMMABLE LOGIC APPLICATION NOTES

November, 1996

by Richard Katz
Electronic Systems Branch
Goddard Space Flight Center
301-286-9705
richard.katz@gsfc.nasa.gov

This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter there will be a focus on radiation-hardened PALs; additionally, more tips for programmable logic will be discussed along with a first section on ‘design and test.’ Many of these tips are based on actual cases in the field at various NASA and industry sites and are fairly common. If you have information that you would like to submit or an area you would like discussed or researched, please give me a call or an e-mail.

Radiation-Hardened PALs

Programmable Array Logic (PAL) devices are a relatively simple, flexible device applicable to a wide range of digital applications and have a programmable AND plane and fixed OR plane. For sequential PALs, flip-flops are included on the device for making structures such as shift registers, counters, etc. There are many types of devices with the 22V10 architecture being relatively standard and flexible; a review of this architecture will not be provided here as this application note will concentrate on radiation-hardened versions of this device. One architectural feature that contributes to the radiation sensitivity of the device is the power-on reset feature; this will be discussed in detail later. There are several providers of PALs for space applications who take different approaches towards meeting the radiation-hardened goal. This note will discuss the UTMC UT22VP10. Unfortunately another manufacturer could not provide all of the data for the summary in time for publication and will be included in the next edition. The following information is based on UTMC literature, military specifications, and an independent test report.

DEVICES AND SPECIFICATION: UTMC refers to their device as the UT22VP10 Universal RADPAL™ and provides their own part numbers for prototype, reduced high-reliability, and Class S. Also, the part is called out in SMD 5962-94754. The device is available in two basic electrical configurations with either TTL-compatible or CMOS-compatible I/O levels.

PROCESS AND TECHNOLOGY: These PALs are built on a triple-level metal 1.2 mm CMOS process with the key technology being the programming element. In general, PALs and other forms of programmable logic use a variety of different techniques for configuration. The UT22VP10 uses a planar amorphous silicon antifuse to provide a low impedance connection between metal layers, making this a one-time programmable, non-volatile device. The vertical antifuse used in these parts consists of an amorphous-silicon layer between layers of titanium tungsten which in turn are between aluminum-silicon-copper metal layers. 5962-94754 specifies a data retention time of 10 years minimum, over the full military temperature range.

PACKAGES: Three package styles are available: 24-lead flat package, 24-lead 300 mil-wide DIP, and a 28-lead quad flat package. ELECTRICAL PERFORMANCE PARAMETERS: Here are some of the key parameters: IDD of 60 mA @ 1 MHz and 120 mA @ 30 MHz for a worst-case pattern; input to output propagation delay = 25 nS; clock to output delay = 15 nS; ts = 18 nS; th = 0 nS; and an external maximum frequency of 30 MHz.

RADIATION TOLERANCE:

Independent testing was performed by the Boeing Defense and Space Group at the LBL cyclotron. The key results are: No latchup was detected at effective LETs as high as 109 MeV-cm2/mg; there was an upset mode where the reset circuitry was hit clearing all 10 data storage flip-flops; upsets were not detected at an LET of 54 MeV-cm2/mg but were detected at LETs of 64 MeV-cm2/mg and higher; and the highest measured cross section was 380 mm2 at an LET of 109 MeV-cm2/mg.

DESIGN AND PROGRAMMING TIPS

CALCULATING PROPAGATION DELAYS FOR ACTEL FPGAs: Design/analysis tools give the capability of setting many parameters; one of these is the speed grade of the parts. In the manufacture and test of these parts, the part is ‘passed’ if a sample circuit known as the binning circuit has a delay not exceeding a specified value. This can be seen by examining SMD 5962-9215601 (A1280), which has electrical performance requirements specifying propagation delay, tPBLH and tPBHL. A careful reading of the SMD shows that only a maximum is specified and if analysis is done assuming that the parts are of the base speed, incorrect results may be obtained since the devices may be considerably faster than anticipated, invalidating the analysis. For example, recently a design was reviewed where the flight parts were bought to a standard speed grade (A1020CQ84E) and the analysts were using the base speed grade for both maximum and minimum calculations. A review of the test data at the manufacturer showed that this lot of parts consisted of approximately 1/2 standard speed grade parts and approximately 1/2 ‘-1’ speed grade parts. All parts were marked as ‘standard’ per the procurement specification and were passed per the test specification.

CHIP EDIT IS BACK: The ChipEdit tool is back in Designer 3.1. This tool has many uses, but one of importance to the designers of spaceflight hardware is the ability to observe the implementation of macros. For SEU performance, a designer may desire that all flip-flops and latches in a particular section be implemented with two C-Module flip-flops. ChipEdit provides an easy to use interface where each flip-flop or latch macro may be selected by it’s reference designator, verifying that it is implemented as desired. ‘C-Module’ flip-flops and latches may be implemented (by the place algorithm) in the combinational portion of an S-Module - ChipEdit provides the information to verify that the dedicated (SEU-soft) S-Module flip-flop is not being used.

WORKSTATION SOFTWARE: Apparently many workstation users aren’t familiar with the ACTmapw and ACTgen programs; these programs are invoked by typing their names at the operating system prompt. ACTmapw provides netlist optimization, VHDL synthesis, PALASM compilation, netlist retargeting and translation (between different families and netlist formats such as .ADL, EDIF, Verilog, and VHDL). ACTgen, based on a form input, automatically generates counters, registers, decoders, multiplexors, adders, subtractors, accumulators, comparators, multipliers, dual port RAMs and FIFOs (supporting embedded SRAM in A3200DX family), I/O blocks, etc. There are subtypes for many of the categories providing different structures (i.e., ripple counter, synchronous counter, LFSR-based counters, etc.), options (i.e., polarity of clock, terminal count, use of enables, etc.) and speed/area trade-offs. This tool is a really big time saver for designers.

ACTGEN TIPS: As noted above, ACTgen is a big time saver for designing many of the standard logic blocks encountered in FPGA design. It is recommended that the design flow include steps to generate schematics from the tool’s output. This is useful for timing analysis, debugging, macro modification, documentation, and, as mentioned in a previous edition, understanding the macros generated by the commercial software; as S-Module flip-flops may be generated for the sequential elements, which have increased SEU susceptibility as compared to C-Module based flip-flops. The ViewLogic software I use for schematic generation, ViewGen, does a fair job and with some editing provides reasonably readable schematics.

Note that many of the ACTgen counter macros can include a terminal count output, similar to standard MSI discrete parts. However, unlike common counter IC’s such as the 54LS16x series, the terminal count is not logically ANDed with the enable, a desirable feature for cascading counter blocks or running circuits at a submultiple of the master global clock frequency. A large number of counter macros have been hand modified with no increase in either module count or in the critical delay path.

LABEL IT: As mentioned above, labels are critical to many applications and analysis processes. A good tip for VHDL designers is to place labels on your processes, component instantiations and assignments; This will allow you to identify signals in the timer (static timing analysis)

FIXING PINS: Fixing pin placement for design modifications has always been critical; after the pins have been FIXED and released for board routing, it is recommended that the I/O placement be manually checked after each run through the place and route tools; this has been learned by many designers the hard way. One design flow that can be used (at least with ViewLogic) is to manually backannotate the pin numbers onto the schematic, resulting in a single drawing that has all of the relevant design information for troubleshooting. This is done by adding a ‘PIN’ attribute to an I/O net and assigning the pin number as the value. Unfortunately, there is currently no way to automatically back annotate this information from the Actel design environment to the ViewLogic schematic. Synopsys users may find pin fixing difficult since the net names may change with each synthesis; in this case use a script file to assign pin placement.

TIMING ANALYSIS: The static timing analyzer is a good tool for timing analysis of designs; for many synchronous designs it makes the internal analysis trivial. This tool, in Designer 3.0 and 3.1 can be used to further speed up the analysis process by invoking it from the top menus: Report->Timing; it will go through and automatically run many of the cases that are of interest. In Designer 3.1, there is now an option that can be set for external setup and hold time analysis, which will automatically calculate these values, eliminating the manual and error-prone task of obtaining propagation and clock delays and then calculating the required set up and hold times.

VIEWLOGIC SAVE: In ViewDraw 7.2 (and probably 7.11) the File->Save command and save icon (floppy disk) save the schematic file but do not perform the checking function and do not update the .WIR file. It is recommended to use the Save + Check command to eliminate any confusion and keep the database up to date and consistent.

DESIGN AND TEST

INTRODUCTION: With the use of PALs and especially FPGAs rapidly increasing, the traditional role of design qualification is moving from the semiconductor manufacturer to the end user, who performs the circuit design, functional and timing analysis, and device programming. Although various tests are done at the programmable device manufacturer on blank parts, it is not sufficient to "flight-qualify" a programmable; indeed, a significant failure level on flight boards has been observed in many organizations. The amount of testing done on a programmable device will depend on the reliability requirements of the mission, the risk level in terms of cost and time, and if design for testability techniques were used. In many of the failures investigated, it was found that the defects could have been detected far earlier in the process, through a combination of methodology, design reviews, and automated test equipment (ATE) testing. ATE testing is superior than what can be done after a programmable has been installed on a board; note that for devices in a quad flat package, removal of the part and ATE testing is difficult, since the leads (up to 256 of them) have been bent and trimmed and will no longer fit test sockets.

The emphasis of this section is to review what can be done with testing and what design engineers can do up front to ease the testing process; this will provide better testing at lower costs, at a small overhead to the flight design. This will be an ongoing series with definitions, strategies, and examples.

ATE CAPABILITY: ATE can extensively test a design and has the following capabilities: it can apply vector sets at high speed to verify device functionality, detect faults, measure leakage currents for the device and I/O pins, drive levels of the I/O pins, propagation delays, pulse width requirements, setup times, and hold times. Additionally, the ATE can be programmed to test the devices over a wide range of operating voltages and temperatures with only a small increase in test time; equivalent tests on a board are sometimes not possible because of the use of regulated power supplies; temperature tests with the flight parts often occur very late in a program where the cost of a failure is typically high in terms of budget and schedule (and many failures are seen there when a different lot of parts is used and temperature excursions are seen for the first time). Likewise, simulators and bench test equipment (BTE) often do not have the capability to change input setup times, hold times and pulse widths.

FAILURE TYPES: Failures of programmables fall into several different categories. While some are screened and detected at the device manufacturer, the nature of many programmables often prohibits a full characterization of every component on the device, even with built-in test circuitry. As a result, many circuits are characterized based on known design limits or sample parts of the chip; for high-reliability applications, this statistical approach is insufficient to meet system requirements. Additionally, for certain classes of programmables, the device will undergo additional high-voltage stresses during programming and may alter the state of the device.

Category 1: Common VLSI microcircuit fault types and their causes are:

• open circuit electromigration, current overstress, broken bond wire or corrosion
  
• short circuit, voids in dielectric layers, voltage overstress of dielectric, inclusions in package
  
• transistor failure, bulk silicon or oxide defects, mask misalignment, impurities or inclusions.

Category 2: Other failures of programmables (many of which have been observed in industry) are:

• no simulation or incomplete simulation;
  
• improper simulation models such as not modeling clock skew;
  
• use of the wrong database for timing analysis (i.e., A1020A models for A1020 parts);
  
• error in the simulation algorithm;
  
• error in the simulation database;
  
• logic design errors resulting in races and hazards.

Observed failures on flight boards show that, for the most part, Category 2 failures are the most frequent, reflecting the users role as part of the device development/ qualification process; additionally, many of the observed failures would have been found earlier in the process with ATE test.

FAULT MODELS: A fault model defines the type, occurrence, and distribution of physical faults that a system may encounter, with examples given in the section above. The single stuck-at model is a popular model because of the accuracy with which it represents the effects of a large class of failures and its tractability as a design tool; the model assumes that faults occur at a single node with the effect that the gate is either stuck at a logic ‘0’ or a logic ‘1’ level. Some faults in programmables are not detected easily or at all by this model. Examples of these are bridging faults, where two independent nodes are connected through an impedance, floating nodes which can produce pattern-dependent or other intermittent faults, dielectric failures which can result in reduced noised margins and overstress, high resistance switches (either pass transistors or antifuses, for example) which produce larger propagation delays, design errors which can produce environmental sensitivities and intermittent operation. Techniques exist for detecting these classes of faults which include IDDQ testing and test vectors based on functional specifications and do not rely exclusively on fault grading.

DESIGN STYLES: Certain design techniques can either make testing difficult or enable simple and efficient test generation. Often, a small increase in circuit area and I/O pin usage helps a great deal Here are a couple of examples to think about; there will be more in the next edition. First, consider the simple divide by 2 circuit implemented by toggle flip-flop to make a clock which drives other circuits such as state machines. This circuit requires no initialization and is very compact and efficient. However, its initial state is unknown so it is difficult if not impossible to determine the device’s state at any period of time; this same problem occurs in simulations with the propagation of the unknown value. However, unlike the logic simulator, there are no internal ‘force’ statements to be executed. A simple fix for this circuit is to apply a reset signal to the clock generating state machine or perhaps, if implemented by a J-K flip-flop, bring the J input off chip through an I/O pin so the flip-flop can be initialized by the ATE. Another common example is a long counter, such as those used to keep mission elapsed time (MET). Requirements for these are often 32-bits which implies 4 billion states, which is impractical to test on the ATE as well as on the board. Design for test techniques here include breaking the counter into 8-bit sections and routing the connections between sections off-chip, resulting in only 256 test vectors; making the counter loadable to easily test all of the bits and logic; or providing a mux which internally breaks the counter in small stages, perhaps running the counter off of a faster clock (for the test engineer who doesn’t want to watch large counters increment with a 1 Hz clock pulse). Another technique to ease the test generation process is to label every component instance and circuit node. One of the outputs of the fault simulations is a list of uncovered nodes and references to machine generated labels which are not visible on the schematic makes the process much more difficult.

HARDWARE INFO

A1020B VARIANTS: The A1020B is processed at either Matsushita (MEC) or Texas Instruments (TI) with most radiation studies being performed on the MEC devices. Tables included in these application notes show that the A1020B is susceptible to latchup. Recent tests on A1020B 1.0 mm device showed, for a particular heavy ion, that the TI devices has a much larger latchup cross-section than the MEC device used; latchup thresholds were not measured for the TI device in this limited test. Latchup currents for both devices ranged from 114 mA to 658 mA; during some runs, multiple latchups were detected. Identification of the A1020x foundries was relatively simple: on the back of the device, an identifier with either a J or a U denoted MEC devices and TI on the back meant a Texas Instruments device. New TI devices do not have the TI marking on the back and used a different code. Further confusing matters, starting about Jan., 1995, Actel began shipping 0.9 mm A1020B devices; no radiation data, to the best of our knowledge, is available on this version of the product. An early prototype of the RH1020, modified from the latest version of the 1020 family, was tested for latchup; no latchup was observed.

MORE FOUNDRIES: Previously, Actel die were manufactured at either Matsushita or TI. With the newer products such as Act 3, XL, and A3200DX families, parts may come from the other foundries such as Winbond and Chartered; some devices such as the A1460A are available from multiple foundries, depending on the speed grade. Take care in the use of radiation data and feel free to contact the author for additional information or clarification.

ACT 3 DEVELOPMENTS: A lot of work is ongoing with respect to the Act 3 devices, the A1460A and the A14100A, as has been reported here previously. Recent work by NASA, Aerospace Corp., the University of Texas, and ESA includes total dose testing, heavy ion testing, and proton testing.

Initial total dose tests of an A1460A from the Winbond foundry had poor results, with approximately 4 krad (Si) looking like a good estimate of that part’s capabilities. Other testing of MEC A1460As showed superior performance: the supply current started to slowly increase at about 15 krads (Si) to an average value of about 20 mA at 50 krads (Si) with no functional failures at this point. The devices were irradiated to 80 krads (Si) and all exhibited functional failure with some devices having large increases in current. A week of room temperature biased annealing resulted in all three devices having an ICC of <10 mA. Currently, several MEC A14100As are being irradiated: at the time of this writing approximately 4 krads (Si) has been accumulated with no significant increase in ICC.

Initial analysis of heavy ion testing showed relatively typical results for C and S-module upsets with some data still to be processed and understood. The key result is that the flip-flops in the I/O cells have relatively poor SEU characteristics, somewhat similar to S-Module dedicated flip-flops. In tests with 300 MeV protons, the A1460A (MEC) S-Modules upset at VCC = 5 VDC and 3.3 VDC; No upsets were detected in I/O modules at VCC = 5 VDC but upsets were detected at VCC = 3.3 VDC.

SEE PERFORMANCE OF FPGAs

As discussed, flight applications of FPGAs are increasing with more designers starting to utilize these devices. In the commercial/military marketplaces devices with new architectures and increasing performance and density levels are constantly appearing. A variety of NASA, ESA, and industry groups are involved in the testing and evaluation of these devices. Recent tests include the RH1280, A1280XL 0.8 µm, A1280XL 0.6 mm, A1280A, A1460A, A14100A, 22V10 PALs, and the NSC CLAy-31. For SRAM-based FPGAs, along with typical data upsets, the configuration of the part may be changed by an SEU in the configuration cell; this has been dubbed Single Event Reconfiguration (SER). Other classes of errors include upsetting on-chip reset circuits as has been seen in a PAL or a TAP controller, an effect believed to have been seen in an FPGA. As usual, at the time of this printing, all of this new data has not yet been analyzed with work ongoing. Some of the results are discussed below, others are included in the tables, and others will be included in the next edition. Please contact the author if any additional information is immediately needed.

PROGRAMMABLES AND PROTONS: Tests have been conducted on several programmables with low upset thresholds for susceptibility to protons and a column to the SEE tables have been added. Additionally proton tests are scheduled for the week of Nov. 18th for the A14100A and A1280XL 0.8 mm devices; A1280XL 0.6 mm devices will also be tested, time permitting. Because of space limitations, full data sets are not presented here; please contact the author for additional data.

MORE ON C-MODULE FLIP-FLOPS: In the last edition, the implementation of C-Module flip-flops and latches was discussed and how the combinational part of an S-Module may be used for flip-flop or latch construction; the dedicated flip-flop in the S-module is bypassed. NASA testing showed that the implementation of C-Module latches did not significantly affect the SEU-hardness of the storage element. Additional data has been reported by ESA which has consistent results with the NASA testing. For reference, in the Act 2 family, flip-flop hard macros using two C-Modules are: DFP1, DFP1A, DFP1B, DFP1D, DFPC, and DFPCA; hard latch macros using a single C-Module are: DLC1, DLC1A, DLE2C, DLE3B, DLE3C, DLP1, DLP1A, DLP1B, and DLP1C.

SUMMARY OF SEE PERFORMANCE OF VARIOUS FPGAs

Notes:

1. A1460A Results similar for routed global clocks and HCLK. Additional testing and analysis is ongoing.
2. Cross-sections are in cm2/flip-flop or bit of configuration RAM.
3. † Latchup detected only with MODE pin high (not flown in this configuration).
3. Single cell, C-Module latches have been tested but the data has not yet been analyzed.
4. Blank cells denote either ‘not measured’ or ‘not yet observed.’
5. †† During latchup, the programmed power supply limit of 800 mA was consistently reached. Repeated latchups resulted in the eventual functional failure of the device.
6. Note that all test organizations do not test identically (i.e., VCC = 4.5V or 5.0V) and the definition of thresholds also vary; the tables are meant as a guide only with more detail available upon request.
7. ††† Analysis showed that high currents were probably not SEL; SER (causing internal device shorts) and snapback are currently theorized for causing the high currents.

The obvious conclusions are:

1. Flip-flops made from two C-modules are relatively hard.
2. Flip-flops made from a single S-Module are relatively soft.
3. TMR techniques are required to make flip-flops very hard ( <10-10 errors/bit-day)
4. A1020B devices are the only Actel devices known to latch up.
5. All the dielectric antifuse devices tested have shown susceptibility to SEDR. The RH1280 and RH1020 appear much more resistant with its redesigned antifuse. Running at 3.6 VDC lowers the bias across the antifuse and no SEDR was observed for A1280A devices under these conditions, with an increase in SEU rates.
6. RH1280 devices offer no significant improvement in SEU performance for C- and S-Modules.
7. With respect to SEUs, Act 3 I/O registers behave similarly to S-Modules while the Act 2 I/O latches behave somewhat similarly to C-Modules.

REPROGRAMMING: One of the many considerations for any programmable device is unintentional reprogramming of the unit in flight. For certain fuse link PROMs, for example, a failure mode seen is open fuses becoming reconnected over time. Many of the newer programmable logic technologies are susceptible to SEE reprogramming. An early example was the EEPROMs, where two types of errors could occur; the first was permanent damage to the device during a write cycle, when high voltage is present in the device; the second is the upset of information in temporary storage registers, while an operation is taking place; both alter the programmed state of the device. For dielectric antifuse devices, permanent damage can occur to the programming element, the antifuse, and is a function of the electric field strength across the dielectric which depends on dielectric thickness and applied bias voltage, angle of the heavy ion with respect to the device, and the LET of the ion; here, damage can be a nuisance current increase, loss of voltage and noise margins, large current increases, decreased reliability from increased current densities, and functional failure of a logic block. Fortunately, the LET threshold for damage is relatively high at normal operating voltages. Amorphous silicon antifuses have yet to be extensively studied for SEE effects, according to the available literature. JTAG 1149.1 enabled devices must have an SEU-hardened TAP controller; otherwise the device state can change into different test modes which can render the part nonfunctional or overstress either the programmable device or other devices on the board.

SRAM-pass transistor based devices, common in many FPGA families, have a number of potential reprogramming effects as a result of a single heavy ion strike. Obviously, the configuration memory itself must be SEU-hardened to prevent either a change of function or the establishment of an illegal configuration which may cause damage. Other effects may include changing the state of the device, perhaps forcing it to re-initialize itself; evidence for this was seen in heavy ion testing of the amorphous silicon-based UT22VP10 PAL, where the device was reset and all flip-flops were cleared to zeros.

Recent heavy ion tests have been conducted on the National Semiconductor CLAy-31 SRAM-based FPGA with several types of errors detected; flip-flop data errors, configuration SRAM errors called single event reconfiguration (SER), and anomalous step increases of current. The step increases were in the range of 25 mA and did not cause the device to malfunction; reloading the device’s SRAM configuration registers reset the current to its initial value without removing power from the device. SER sensitivity can be characterized for a device; an example for the CLAy-31 is shown below, at VCC = 5 VDC and T = 25°C.

PROGRAMMING, DEBUGGING, and TESTING TIPS

PROGRAMMING AND S/W UPDATES: Many of us are updating our hardware platforms, operating systems, and programming software (i.e., moving from ALS 2.3.2 to Designer 3.1). Problems have been noticed with some of the older SCSI adapter cards which communicate with the Activator 2 and Activator 2S. In particular, the 8-bit Western Digital and Trantor cards would work in various degrees and have been superseded by the Adaptec cards. On my systems, the Western Digital card produced lots of headaches with Designer 3.0 and a Trantor card seems to work fine programming in DOS with Designer 3.1 but will not work with APSW in Windows, which was written using Adaptec’s ASPI driver, which only speaks to Adaptec’s ASPI layer. Additionally, Actel has stated that under Windows NT, APS2 (the DOS program) does not function properly because the DOS shells under NT are separated from the hardware by a software layer and that APSW works fine if you are using an Adaptec card. A last issue is that when upgrading cards, pay careful attention to the connectors; the Activators and cards come with a variety of connectors and a cable upgrade may be necessary also. So, be careful when upgrading and check out your systems prior to programming flight parts.

TOTAL DOSE PERFORMANCE AT LOW DOSE RATES - UPDATE

Testing of Actel A1280As has been completed under a number of dose rates by a variety of organizations. While there has been some variability, there has been no dramatic effect in performance vs. dose rate, down to approximately 0.01 rads (Si) per second. Rockwell has tested a particular lot of A1280s ( 1.2 µm) at a rate of approximately 0.005 rads (Si) per second with results that indicated either different effects or an unusually ‘hard’ response for this type of device. NASA testing of an A1280A sample at 0.002 ± 10% Rads (Si) per second, from a lot with a known radiation history has continued, under static bias, to approximately 30 krads (Si); post-exposure testing showed an increase of ICC by approximately 4.5 mA; the device passed all functional and parametric tests and good voltage margins were maintained. Several A1020Bs, also from well-characterized lots are being irradiated at similar dose rates with one of the devices showing considerable leakage levels at a fairly low dose. Further low dose rate testing will use A14100A, A1280A and A1280XL 0.8 mm devices.

ACKNOWLEDGMENTS and REFERENCES

NASA/GSFC - Ken LaBel (http://flick.gsfc.nasa.gov/radhome.htm)

NASA/JPL - Gary Swift

Actel Corp.: JJ Wang, Jay McKibben.

ESA: Document SE/REP/0047/K, September 18, 1996 "UTMC UT22VP10 PAL Single Event Effects Test Report," 9-5574-WEW95-139, J. Wert/Boeing Defense & Space Group, June 9, 1996.

Tom Karygiannis, Aeronautix, LLC.

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