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PROGRAMMABLE LOGIC APPLICATION NOTES

July, 1996

by Richard Katz
Electronic Systems Branch
Goddard Space Flight Center
301-286-9705

This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter the focus was to be on radiation-hardened PALs; however, because of time constraints, that has been postponed to the next issue. This issue will focus on results of testing the RH1280 and other manufacturers FPGAs as well as some more design tips. Many of these tips are based on actual failures in the field at various NASA and industry sites and are fairly common. If you have information that you would like to submit or an area you would like discussed or researched, please give me a call or an e-mail.

DESIGN TIPS

CLOCK SKEW: Failure to properly manage clock skew is a major source of failures in FPGA designs. There have been a number of instances where ‘proven’ designs have failed when the flight devices were installed into ‘working systems’ or intermittents would be eliminated by re-routing a device. The causes of these failures was twofold: improper understanding of clock skew inside FPGAs and models which did not accurately reflect delays within the device.

The Actel anti-fuse based FPGAs provide high-speed, low-skew global and quadrant clocks. There is one global clock for the 1020 devices, 2 global clocks for the 1280’s, 3 global clocks for the 1460/14100’s (two routed, 1 dedicated), and up to 6 clocks (two global, 4 quadrant) in some models of the A3200DX family. For the Act 1 A1020x devices, the user can instruct the placement and routing software how much effort to expend on clock balancing, trading off clock skew for system performance. The other series devices have improved clock networks where this is not necessary. So, by appropriate ‘balancing’ in the Act 1 family and normal usage of the global clocks in the other devices, clock skew is normally not a problem. Adequate timing margins can easily be calculated using TIMER.

When regular signals are used as clocks, care must be taken to ensure that setup and hold times are guaranteed to be met. Routing clock signals inside of an FPGA is not the same as routing a clock on a printed circuit board (PCB). Signal propagation delay is often negligible on a PCB and is frequently neglected as a major source of clock skew. However, for example, proper clocking is sometimes difficult when using CD40xxB logic where clock signals may have long transition times and flip-flops can have threshold varying from 30% to 70% of VDD. This can result in the parallel clocking problem where hold times may not be met since the data to the flip-flop may change prior to the clock signal reaching the logic thresholds. Since signals routed in an FPGA must propagate through a number of segments and antifuses, the arrival of the clock at various points on a network will not occur at the same time. This results in clock skew and an equivalent problem to the CD40xxB parallel clocking problem.

Certain structures are extremely sensitive to this. For example, shift registers, which have little or no logic between stages, are very prone to failure. A change in either supply voltage or temperature can cause problems to appear and disappear. In general, any structure that employs parallel clocking needs to be carefully looked at. Also, soft macros appear to have a common clock input. They don’t. It is a soft macro and the clock will propagate down a clock tree with skew between the leaves if not on a low-skew clock bus. So, easy to use macros like the TA161 counter or macros generated by ACTGen which are guaranteed to be correct by construction can fail if improperly clocked although they appear fine on the schematic.

Compounding this problem are the models used to simulate the designs. At two different contractors these issues were explored in depth to analyze their failing systems with both groups performing full simulations. However, they used a logic simulator to perform their timing analysis and either didn’t use or improperly used TIMER. In both cases, however, the logic simulator did not model the clock skew between flip-flops, assumed all clocks arrived at the same time, and ‘passed’ the circuits.

There are a number of different solutions to these types of problems and some will be briefly discussed here. First, if the design can be made synchronous, use the global clocks. The hard macros supplied by Actel minimize the pain caused by the architectural limitation of a small number of low-skew clocks. These macros include flip-flops with enables and flip-flops with multiplexors on the inputs. Another approach is to utilize a structure where flip-flops that communicate pass data between opposite edges of the clock. This moves a clock skew problem into a clock width consideration and possibly a device utilization issue. A more compact solution but with more complexity is to use a two-phase non-overlapping clock structure with one-module latches. Another technique is, where possible, to eliminate the use of synchronous counters and use ripple counters or a hybrid counter where the first stage is synchronous which feeds the remaining stages that operate in a ripple mode.

CALCULATING PROPAGATION DELAYS FOR ACTEL FPGAs: Calculating propagation delays with a static timing analyzer like TIMER is critical for ensuring that there are no races, setup and hold times are met, etc. Now, with TIMER, it is quite easy to determine minimum and maximum delays for sets of paths. However, it should be noted that in certain cases the minimum numbers reported by TIMER need to be ‘adjusted.’ The calculations done for the minimums are not worst-case minimums and may in fact be longer than the actual delays. So, for minimum paths, a derating factor must be applied. These can be found in the 1995 Actel Data Book on page 10-57 in an application note titled "Setup and Hold Time Analysis Using the Actel Timer." Also included in this note is useful equations for determining the parameters. For example, the derating for a A1020 would be 0.7 for all paths. For the A1280A, there is a 0.78 derating for all combinatorial paths and a 0.85 derating for the routed global clock.

PERFORMANCE COMPARISON BETWEEN VARIOUS FAMILIES: A reference test design was implemented in three different technologies for performance comparisons. The same data base was used for all designs with no placement or routing changes. Additionally, common ‘environmental’ conditions were used. These are: pre-rad, VCC=4.5VDC, standard speed grade, worst-case process, and a junction temperature of 85°C. The three devices simulated were the A1280A, the A1280XL (0.6 µm), and the RH1280. As can be seen from the table below, there are significant overall speed differences. One comes from the technology as seen in the Reg -> Reg delays and a more significant increase in performance comes from the I/O cells as shown by the I/O performance. All data is in nanoseconds in a min/max format. The simulations were performed using Designer 3.0.1s on a PC.

PIN ASSIGNMENT ERRATA: In the 1994 data book Military Section, there is an incorrect pin assignment for the A1280A CPGA176 package. The letter sequence calls out ABCDEFGHJKMNPQR. It should be ABCDEFGHJKLMNPR.

UNUSED INPUTS: The termination requirement for unused inputs was addressed in the October 1995 issue of EEE Links. One design that was reviewed treated the unused pins of the A1020 devices like inputs of a regular CMOS device and tied all pads on the PCB for unused pins to GND. Now, since the unused pins are configured as either outputs driving low or as high impedance, this seems to be logically fine. However, upon the application of power, pins may act as outputs driving high and can source considerable current. So, along with the startup current transient associated with the Actel devices, current will be sourced to ground through these unused pins as the device starts and stabilizes [see "A Power-On Reset (POR) Circuit for Actel Devices].

HIGH LEVEL DESIGN: High level design methodology is growing in popularity. However, it is strongly recommended that the design flow include schematic generation for any synthesized or optimized blocks. This aids in the communication with tools for static timing analysis, for instance, as well as troubleshooting. Also, the tools may do something considerably different than the designer anticipates, with an impact on proper operation of the device and timing margins, particularly for asynchronous circuits.

PRESETS and CLEARS: For discrete parts such as the standard 54LS74A, it has been observed that some designers assert both the PRESET and CLEAR simultaneously. Some sequential macros, such as the DFPC, have the capability for asserting both of these asynchronous inputs. While the 54LS74A guarantees that the output of the device will be a logic ‘1’, tests on an A1020B showed that asserting both the PRESET and CLEAR of the DFPC resulted in a high frequency oscillation of approximately 150 MHz!

DESIGNER 3.0 COMBINER: In Designer 3.0, the default behavior of the combiner function has been changed from earlier versions and a description of the current operation of this software is given in Actel’s User Guide. While the goal of the Combiner is to give faster, denser, more routable designs, this may impact circuit performance. For instance, a string of buffers inserted to create a delay (ugly, but sometimes needed) will be collapsed into a single element which is logically equivalent. However, if the delay is needed to create adequate set up times for an external signal interface, for example, the macros will be deleted without warning. This will be detectable, however, when running the static timing analyzer TIMER. Also note that there is a bug in the generation of the .cob file where deleted macros are not always recorded. To instruct the combiner not to perform this function, attach the attribute ‘PRESERVE’ to the net being driven by the macro that is desired not to be collapsed.

SEE PERFORMANCE OF FPGAs

As discussed, flight applications of FPGAs are increasing with more designers starting to utilize these devices. In the commercial/military marketplaces devices with new architectures and increasing performance and density levels are constantly appearing. A variety of NASA and industry groups are involved in the testing and evaluation of these devices. Recent tests include the RH1280, A1280XL 0.8 µm, A1280A, A1460A, Quicklogic FPGAs, Atmel AT6002, Xilinx XC3090A, and the AT&T ATT2C04-2. For SRAM-based FPGA’s, along with typical data upsets, the configuration of the part may be changed by an SEU in the configuration cell; this has been dubbed Single Event Reconfiguration (SER). At the time of this printing, all of this new data has not yet been analyzed. Some of the results are discussed below, others are included in the tables, and others will be included in the next edition. Please contact me if any additional information is immediately needed.

ACTELS AND PROTONS: Tests have been conducted on several models of the 1280 family for susceptibility to protons. Devices that would not upset under normal operating voltages (4.5 VDC RH1280 Proton Test Results

RH1280 AND SEDR: The antifuses on the RH1280 have been modified from the original commercial/military devices to harden them to Single Event Dielectric Rupture (SEDR). Essentially, the devices were thickened to decrease the electric field strength. The different thickness antifuses are ~85 Å for the commercial military devices and about 100 Å for the RH1280 (oxide-equivalent dimensions). Product testing by the foundry did not detect any evidence of SEDR. An initial NASA evaluation did detect SEDR and determined thresholds at several points. The data set taken was intentionally small so as not to seriously damage the parts; further data will be taken to get an accurate cross-section, which appears to be small. For S/N 068, the SEDR threshold for LET=37 was between 5.7 and 5.8 VDC, giving between 200 and 300 mV of margin for this part at room temperature. For S/N 063, the SEDR threshold for LET=53 was approximately 4.7 VDC, also at room temperature.

C-MODULE FLIP-FLOPS: In the last edition, the SEU performance of the various types of flip-flops was discussed. To expand on this, it should be noted that flip-flops implemented using ‘C-Modules macros’ may in fact be implemented in the combinational part of an S-Module. It is guaranteed by the design software that the dedicated flip-flop in the S-Module will not be used. This is critical since flip-flops made from C-Modules have superior SEU performance to those made from the dedicated flip-flops in the S-Modules. Testing appears to confirm this. Recently, a new chip design (CMOD2) has been tested at BNL to verify this and to quantify the SEU performance of the various configurations with data analysis expected to be completed in several weeks. For instance, an edge-triggered ‘C-Module’ flip-flop in a x1280y may be implemented by two C-Modules, two S-Modules, or a combination of S- and C-Modules. Also, single ‘C-Module latches’ may be implemented in a C-Module or the combinational part of a S-Module.

SUMMARY OF SEE PERFORMANCE OF VARIOUS FPGAs

Notes: 1. A1460A Results same for routed global clocks and HCLK.
2. Cross-sections are in cm2/flip-flop.
3. * Latchup detected only with MODE pin high (not flown in this configuration).
3. Single cell, C-Module latches have been tested but the data has not yet been analyzed.
4. Blank cells denote either ‘not measured’ or ‘not yet observed.’

The obvious conclusions are:
1. Flip-flops made from two C-modules are relatively hard.
2. Flip-flops made from a single S-Module are relatively soft.
3. TMR techniques are required to make flip-flops very hard ( <10-10 errors/bit-day)
4. A1020B devices are the only Actel devices known to latch up.
5. All the dielectric antifuse devices tested have shown susceptibility to SEDR. The RH1280 appears more resistant with its redesigned antifuse. Running at 3.6 VDC lowers the bias across the antifuse and no SEDR was observed for A1280A devices under these conditions.
6. RH1280 devices offer no significant improvement in SEU performance for C- and S-Modules.
7. 3.3 volt operation eliminates SEDR from Actels and increases SEU rate.

PROGRAMMING, DEBUGGING, and TESTING TIPS

HOT SOCKET: When using the debugger for either troubleshooting or running test vectors care should be taken not to remove parts when in the debugger menu system. In this state, a part will be removed from a powered socket and is not recommended.

BUG: It has been seen for certain lots of parts that the Activators will fail functional vectors on correctly working devices. This has been noticed in some A1280A lots. Troubleshooting has revealed that the Activator has trouble starting the parts with the voltage only reaching approximately 3.25 VDC. Additionally, current probing has found large (several hundred milliamp) current pulses going into the part in this mode. Lastly, when running the CHECKSUM command from the main menu, trouble starting the part was also observed with the DCLK input signal being clamped as a result of the reduced supply on the FPGA. Actel is currently working this problem.

HANDLE WITH CARE: The QFP172 package, used for the 1280 series, should be handled with care. A number of devices have come in with bent corners and these have had alignment problems with the Enplas ZIF sockets used on the Activators and test fixtures. The ‘vacuum wand’ should be used for removing parts from these sockets.

VERIFY ALL OF THE SPECIAL PURPOSE PINS. A number of cases have been seen where, for instance, the MODE pin has been left floating. This is very bad. As discussed, test procedures should ensure via direct measurement that the MODE pin is grounded. Additionally, pins such as VPP, VSV, VKS, etc. should be checked as well as all power and ground pins. A completed instrument is currently being disassembled to fix floating MODE and VPP pins.

DYNAMIC BURN-IN: Post-programming dynamic burn-in is a topic extensively discussed. Actel devices and SEI RAD-PAK devices both undergo dynamic burn-in with varying (widely) degrees of coverage. Along with the degree of coverage on the devices, there is also the fact that the parts are subject to relatively high voltages during programming. Responding to this, NASA has developed post-programming dynamic burn-in boards for the 1020 and 1280 families of parts. For each model, both quad-flat pack and pin grid array ZIF sockets are provided.

PACKAGE CONVERTERS: NASA has developed package converters for the QFP84 and the QFP172 flat packs to make them appear to be PGA84’s and PGA176’s. The converters are designed to be compatible with the ‘-repackage’ command thus requiring no new placement and routing steps, preserving the database developed using PGA breadboard parts. Also, they give the capability to utilize existing ATE fixtures, radiation bias boards, etc., with quad flat pack devices. Lastly, they are useful for ‘at-speed’ testing of flight devices prior to lead forming and installation on the flight card.

ESD and LIDS: For a number of the Actel products, the lids are not grounded. It is imperative that proper precautions be taken to ensure that the parts are not damaged by ESD. There has been a number of cases where parts have been damaged in test. Failures have been reported in a burn-in oven others were on a parts tester at electrical test.

TOTAL DOSE PERFORMANCE AT LOW DOSE RATES

Testing of Actel A1280As has been completed under a number of dose rates. While there has been some variability, there has been no dramatic effect in performance vs. dose rate. Rockwell has tested a particular lot of A1280’s ( 1.2 µm) at a rate of approximately 0.005 rads (Si) per second with results that indicated either different effects or an unusually ‘hard’ response for this type of device. In particular, they recorded data that showed only a minimal increase in ICC: after 30 krads (Si) a delta of 2.1 mA and after 60 krads (Si) a delta of 3.2 mA.

Samples were tested at NASA/GSFC and at NASA/CalTech-JPL for a variety of dose rates with generally repeatable results for the A1280A product. However, none of the previous work tested at the 0.005 rads (Si)/sec rate. The first in our series of very low dose rate testing exposed an A1280A, PG176B, D/C 9424, U1H-82#21, PC423026 at a rate of 0.01 rads (Si) per second with a static bias. The total dose response of the device was similar to that obtained with higher dose rates. After approximately 10 krads (Si) of exposure, a delta current of approximately 70 mA was measured and at approximately 7 krads (Si) a delta current of 20 mA was measured.

Currently, another sample is being tested at 0.002 ± 10% Rads (Si) per second, also under static bias. To date the device has been exposed to 7.2 krads (Si) with no change in supply current. Another device from the same lot of parts will be irradiated at 0.005 Rads (Si) per second using a dynamic bias board.

SUMMARY OF TOTAL DOSE PERFORMANCE

The charts below compiled by Gary M. Swift of CalTech/JPL show a summary of test results for many specific lots of A1280A’s. A similar summary of A1020x’s will appear in the next edition. Note that many components in the table do not include the results of annealing; thus, certain parameters such as ICC and transient start-up currents will be less after annealing than is seen in the table. Post-annealing measurements are being made now.

Below is an example of the startup current characteristics of an A1280A. The first picture is from the control sample; the second is a device after 7 krads (Si) of radiation, post annealing. The two curves in the photo represent VCC at 1 V/DIV and ICC at 200 mA/DIV.

A1280A CONTROL SAMPLE

A1280A, 7 kRads (Si), Post-annealing

Voltage @ 1V/DIV, Current @ 100 mA/DIV

Data Summary available in .PDF Format.

MISCELLANEOUS

Future work includes completing the characterization of the RH1280 and the A1460A. Additionally, testing is planned for the A14100A and the A32200DX devices.

A collection of papers and reports about Actel FPGAs will soon be released as a NASA report titled "Evaluation of Commercial Technology in Spacecraft Radiation-Hardened/High-Reliability Applications: A Case Study Using Field Programmable Gate Arrays." Contact either myself at GSFC or Gary Swift of CalTech/JPL (818) 354-5059 for availability.

ACKNOWLEDGEMENTS and REFERENCES

NASA/GSFC - Ken LaBel (http://flick.gsfc.nasa.gov/radhome.htm)
NASA/JPL - Gary Swift

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Last Revised: January 09, 2002
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