Issue-
The 256K SRAM in the 28 lead flat pack does not provide a satisfactory ground connection for operation in TTL mode for the Read conditions listed in datasheet HX6256.
Background-
The issue arises due to inadequate on-chip power bussing. Various address changes, pre-charge pulses, and switching outputs create a considerable amount of drawdown on the power bussing. Functional performance is achieved by having adequate grounding on the package (ex. Maintaining equivalent package and board grounds). The 28-lead package in correlation with the 256K SRAM has demonstrated on-chip ground bounce, which occurs when switching all addresses simultaneously; this situation could cause the device to enter into a state of oscillation.
Non-Conformance-
Toggling the NOE pin coincident with an address change could cause the chip to enter oscillation if all of the inputs are toggled together.
Corrective Action-
Analysis demonstrates that delaying the NOE transition for 15nS following an address change will allow the part to operate correctly. In addition when enabling the chip NCS should occur at least 15nS prior to the NOE transition. The delay of NOE provides enough time for the noise created by the address change or the enabling of NCS to dampen out.
Note: Analysis highlighted that connecting the VSS chip capacitor to the board VSS will shunt the inductance of the package. This is not a fix, but will dampen the noise and improve performance margin.
Home
Last Revised: March 15, 2002
Digital Engineering Institute
Web Grunt: Richard Katz