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A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Tutorials for Programmable Logic and Military/Aerospace Systems

Logic Design: Clocking, Timing Analysis, Finite State Machines,
and Verification

Presented at the

2002 MAPLD International Conference
Laurel, MD
September 9, 2002

Abstract

The fundamental theme of this seminar will be the design and verification finite state machines for high-reliability applications. The starting point for any synchronous sequential circuit design and analysis is the clock. Clock structures and characteristics, both at the device and application level, will be discussed and their impact on circuit topologies and timing analysis. Starting with the straightforward single-phase, single-edge, low-skew global clocks, different clock structures will be explored for different design goals such as low-power and high-speed. Finite state machines will be covered in detail from two perspectives: the topologies logic as well as applications. Examples of topologies to be covered will include Gray, one-hot, sequential, LFSR, and others. Applications to be covered include synchronizers, arbiters, controllers, and others. Analysis will be performed to determine the robustness of each solution. The results of the analysis will lead to a discussion of error detection and correction and the trade-offs; e.g., some circuits have a higher probability of error but permit 100% detection of all single bit errors. A discussion of error detection and correction methods will show various techniques as well as trade-offs. For example, should the monitoring circuits be located at the lowest possible level or the system level? This will be shown to be a function of the state machine's structure and circuit application.

Course Outline (.ppt version; click for .pdf version)

Introduction

Clocking

• Clock Distribution Topologies
• Clock Skew
• DLLs and PLLs
• Clock Structures: Real Devices
• Microprocessor Clocks
• Clock Timing and Skew: Real Devices
• Clock Upset
• Miscellaneous Clock Topics

Finite State Machines, Low Level

• Basic Finite State Machines
• FSM Implementation (1)
• Event Counters
• Gray Codes
• Linear Feedback Shift Registers
• SEU Hard Counters
• Resetting Finite State Machines
• Memory Controllers
• FSM Implementation (2)

Finite State Machine, Systems Level

• System Timing Analysis
• System Level Error Hhandling
• System Protection: Watch Dog Timer
• Metastablestates
• Hardware as Software
• Pipelining

.pdf version (courtesy of Paul S. Graham, Los Alamos National Laboratory)

Course Outline

Introduction

Clocking

• Clock Distribution Topologies
• Clock Skew
• DLLs and PLLs
• Clock Structures: Real Devices
• Microprocessor Clocks
• Clock Timing and Skew: Real Devices
• Clock Upset
• Miscellaneous Clock Topics

Finite State Machines, Low Level

• Basic Finite State Machines
• FSM Implementation (1)
• Event Counters
• Gray Codes
• Linear Feedback Shift Registers
• SEU Hard Counters
• Resetting Finite State Machines
• Memory Controllers
• FSM Implementation (2)

Finite State Machine, Systems Level

• System Timing Analysis
• System Level Error Hhandling
• System Protection: Watch Dog Timer
• Metastablestates
• Hardware as Software
• Pipelining

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Last Revised: October 02, 2002
Digital Engineering Institute
Web Grunt: Richard Katz