Some of the sections are still under development. It is expected that all of the material will be updated and augmented over time. Comments, corrections, case studies, and ideas are welcome. All files are in .ppt format. If you need another format, please let me know. --rk (rich.katz@gsfc.nasa.gov)
- Introduction
- Special_Pins
- Input_Stages
- The Startup Transient
- Hazards
- Asynchronous_Logic
- Signal_Quality
- Fail Safe Logic
- Reliability
- Power_Switching
- Redundancy
- Diverse_Design
- Configuration_Control
- Clock_Skew
- Processor_Self_Test
- Metastable States
- Finite_State_Machines
- VHDL_And_SW_Issues
- Funcitonal Interrupt
- Specifications
- Simulators
- Verification
- Conclusion
Home
Last Revised: January 09, 2002
Digital Engineering Institute
Web Grunt: Richard Katz