Abstract
Many modern systems require high levels of digital signal processing to meet their functional and performance objectives. While general-purpose processors are increasing in speed and some DSP processors are becoming available, machines based on these technologies are not optimized for power and are limited in performance as a result of the general purpose nature of the architecture and the limited parallelism available in the hardware. Programmable logic based solutions can implement solutions tailored for the problem and make extensive use of both parallelism and pipelining techniques. The key structures in various processing algorithms and arithmetic functions will be analyzed. Then, these functions will be mapped onto available device architectures, comparing performance potential and implementation issues and identification of critical paths in each device type. Lastly, for compact implementations, the use of high-speed devices and bit-serial circuits will be discussed.
Home - NASA Office of Logic Design
Last Revised: March 06, 2003
Digital Engineering Institute
Web Grunt: Richard Katz
