This page is used for the official dissemination of test status, results, and reports.
The NASA Office of Logic Design independent accelerated reliability test of Actel FPGAs is in progress and will evaluate A54SX-A, RTSX-S, and RTSX-SU devices. The RTSX-S (MEC) and the RTSX-SU (UMC) are both 0.25 µm devices. A54SX-A devices are produced at both MEC (0.25 µm) and UMC (0.22 µm); only UMC A54SX-A devices are planned for evaluation at this time.
This is an accelerated test and the devices are subjected to higher stress levels than seen in our applications. Thus, devices under test (DUTs) are subjected to environmental conditions ranging from -55 ºC to 125 ºC with each step being 250 hours in duration. The first 1,250-hour segment consists of 250 hours of -55 ºC and 1,000 hours of 125 ºC exposure. Additionally, other parameters are stressors, such as increased fanout, number of simultaneous switching outputs, amount of undershoot, and the supply voltage. As the test proceeds, the DUTs will be subjected to additional test hours, increased voltage stress, increased node switching frequencies, an increase in the number of simultaneous switching outputs, and an increase in the amount of simultaneous undershoot.
Please note that the "Industry Tiger Team," led by the Aerospace Corporation, utilizes a different test vehicle and protocols and has different objectives than this test conducted by NASA. As a result, there are a number of differences between the tests. A description of the test vehicles can be found in:
"RTSX-S and RTSX-SU Reliability Test Vehicles"
Daniel K. Elftmann1, Richard Katz2, and Igor Kleyner2
1Actel Corp.
2 NASA Office of Logic Design
Presented at the 2004 MAPLD International Conference, September 8-10, 2004, Washington, D.C.
Related information
"Actel RTSX-S, RTSX-SU, and SX-A Briefing," September 22, 2004, NASA Goddard Space Flight Center
"Actel RTSX-S and RTSX-SU Briefing," July 13, 2004, NASA Goddard Space Flight Center.
"OLD News #16: Testing of Actel SX-A and RTSX-S Programming Algorithms," May 17, 2004
"OLD News #15: Actel SX-A and RTSX-S Programmed Antifuses," March 17, 2004
"OLD News #14: Testing and Application of Modern Microelectronic Devices: Do's, Don'ts, and Failures," November 19, 2003
"Actel SX-A, RTSX-S, and RTSX-SU FPGAs in Mission- and Safety-Critical Systems: A Summary and Snapshot of a Dynamic Situation," November 3, 2004.
Briefing: Independent NASA Test of RTSX-SU FPGAs, held February 16, 2005.
Testing Summary: NASA Test of Actel SX-A, SX-S and SX-SU FPGAs
"ESD Sensitivity of Actel RTSX-SU Field Programmable Gate Arrays," March 10, 2005
Briefing: Independent NASA Test of FPGAs (May 11, 2005)
Proceedings of the "Briefing: RT54SX-S, RTSX-SU, RTAX-S, and Eclipse FPGAs for Spaceborne Application (May 10, 2006).
NASA2 Design, used for KU3 and KU4. (May 12, 2006).
KM3 and KM4 will be MEC devices with the modified new algorithm (V3.89).
KU3 and KU4 will be UMC devices, new silicon revision, with both the UMC Modified Algorithm and the SAL.
KU3 and KU4 will use the NASA2 Design for the DUT pattern.
Batch KU1: 150 RTSX32SU-CQ208B (D122H1) FPGAs have been programmed (October 16-17, 2004). (anomalies)
ATE Data: -55 °C, 25 °C, and +125 °C, Week of October 18, 2004
Test Step KU1-1
Start of Test: October 23, 2004
Duration: 250 hours, Chamber #1
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC;
ATE Data, November 5, 2004: All devices pass.
Test Step KU1-2
Start of Test: November 5, 2004
Duration: 250 hours, Chamber #1
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC;
ATE Data, November 22, 2004: All devices pass.
Test Step KU1-3A
Start of Test: November 24, 2004
Duration: 250 hours, Chamber #3 - Step terminated at the 115 hour point for a safety shutdown.
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = -55 ºC;
ATE Data, December 16, 2004: One delta delay anomaly (50956). Resolved Single S antifuse failure.
Test Step KU1-3B
Start of Test: February 4, 2005, Chamber #2
Duration: 55 hours
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = -55 ºC;
ATE Data, February 22, 2005: One VIH anomaly under investigation.
Test Step KU1-3C
Start of Test: February 11, 2005.
Duration: 80 hours, Chamber #2
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = -55 ºC;
ATE Data, February 24, 2005. All devices pass.
Test Step KU1-4
Start of Test: February 25, 2005.
Duration: 250 hours, Chamber #1
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC;
ATE Data, March 14, 2005. All devices pass.
Test Step KU1-5
Start of Test: March 9, 2005.
Duration: 250 hours, Chamber #1
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC;
ATE Data, April 4, 2005. One VIH anomaly (S/N 50992) under investigation.
Test Step KU1-6
Engineering run has been performed at VCCA = 3.2V, +125 °C.
Duration: 250 hours, Chamber #1
Electrical Environment: VCCA=3.0V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
ATE Data. All devices pass.
Test Step KU1-7
Duration: 250 hours, Chamber #1
Electrical Environment: VCCA=3.0V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = -55 ºC
ATE Data. All devices pass.
Batch KU2: 150 RTSX32SU-CQ208B (D122H1) FPGAs have been programmed (November 4-9, 2004). (anomalies)
ATE Data: -55 °C, 25 °C, and +125 °C
Test Step KU2-1
Start of Test: November 23, 2004
Duration: 250 hours, Chamber #1
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
ATE Data, December 8, 2004: All devices pass.
Test Step KU2-2
Start of Test: December 8, 2004
Duration: 250 hours, Chamber #1
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
ATE Data, December 23, 2004: One can not duplicate anomaly being monitored.
Test Step KU2-3
Start of Test: December 23, 2004
Duration: 250 hours, Chamber #1
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
ATE Data, January 9, 2005. All devices pass.
Test Step KU2-4
Test Step KU2-5
Start of Test: April 4, 2005
Duration: 250 hours, Chamber ...
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = -55 ºC
ATE Data. One VIH anomaly (S/N 50958) under investigation from tri-temperature cold test.
Test Step KU2-6
Engineering runs are currently being performed as an aid to setting the increased stress levels for this test step. The conditions will be -55 ºC and VCCA=3.2V
Duration: 250 hours, Chamber #TBD
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = -55 ºC
ATE Data: All devices pass..
Test Step KU2-7
Duration: 250 hours, Chamber #TBD
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
ATE Data: All devices pass..
Batch KU3:
Stimulus: CLKA / CLKB = 8 MHz (HTOL); CLKA / CLKB = 16 MHz (LTOL)
Batch KM1: 150 RT54SX32S-CQ208B FPGAs (New programming algorithm) - (anomalies)
Test Step KM1-0
Programming complete. December 28, 2004 to January 10, 2005.
ATE Data: -55 °C, 25 °C, and +125 °C. Anomaly: S/N 37887: Functional Failure at Cold Temperature Test: Damaged K antifuse.
Test Step KM1-1A
Start of Test: January 19, 2005.
Duration: 50 hours, Chamber #1.
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
ATE Data, January 30, 2005. All devices pass.
Test Step KM1-1B
Start of Test: January 26, 2005.
Duration: 200 hours, Chamber #1.
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
ATE Data: February 12, 2005. Anomaly S/N 37858 failed functional array testing. Damaged K antifuse.
Test Step KM1-2
Start of Test: February 7, 2005.
Duration: 250 hours, Chamber #1.
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
Test Step KM1-3
Start of Test: March 1, 2005.
Duration: 250 hours, Chamber #1.
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
ATE Data, March 21, 2005. One VIH anomaly (S/N 38057) under investigation.
Test Step KM1-4
Start of Test: March 21, 2005.
Duration: 250 hours, Chamber #1.
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
Status: Complete, no failures.
Test Step KM1-5
Start of Test: April 19, 2005.
Duration: 250 hours,
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = -55 ºC
Location of DUTs in Chamber
ATE Data, May 1, 2005. One tPD anomaly (S/N 37990) under investigation. Damaged F antifuse.
Batch KM2: 150 RT54SX32S-CQ208B FPGAs (New programming algorithm) - (anomalies)
Programming complete.
ATE Data: -55 °C, 25 °C, and +125 °C. ATE report in preparation.
Test Step KM2-1A
Start of Test: March 17, 2005.
Duration: 50 hours, Chamber #1.
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
Status: Complete, no failures.
Test Step KM2-1B
Start of Test: April 8, 2005.
Duration: 200 hours, Chamber #1.
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
Location of DUTs in Chamber
Status: Complete, no failures.
Test Step KM2-2
Start of Test: April 21, 2005.
Duration: 250 hours, Chamber #1.
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
Location of DUTs in Chamber
Status: Complete, no failures.
Test Step KM2-3
Start of Test: May 16, 2005.
Duration: 250 hours, Chamber #1.
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
Location of DUTs in Chamber
Status: Complete, no failures.
Test Step KM2-4
Start of Test: June 8, 2005.
Duration: 250 hours, Chamber #1.
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
Location of DUTs in Chamber
Status: One tPD Anomaly: (S/N 38014) - Failed single S-type antifuse.
Test Step KM2-5
Start of Test: July 13, 2005.
Duration: 250 hours, Chamber #1.
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = -55 ºC
Location of DUTs in Chamber
Status: Test complete. S/N 27869 failed, I/O monitor not toggling.
Batch KM3: 150 RT54SX32S-CQ208B FPGAs (Modified new programming algorithm - 3.90 (built 0623)) - (anomalies)
Programming complete.
ATE Data: -55 °C, 25 °C, and +125 °C. No failures.
Test Step KM3-1
Duration: 250 hours
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
Location of DUTs in Chamber
Status: Complete, no failures.
Test Step KM3-2
Duration: 250 hours
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
Location of DUTs in Chamber
Status: Complete, no failures.
Test Step KM3-3
Duration: 250 hours
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
Location of DUTs in Chamber
Status: Complete, no failures.
Test Step KM3-4
Duration: 250 hours
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 125 ºC
Location of DUTs in Chamber
Status: Complete, no failures.
Test Step KM3-5
Duration: 250 hours
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = -55 ºC
Location of DUTs in Chamber
Status: One anomaly, array shift register failure, F antifuse.
Batch KM4: 150 RT54SX32S-CQ208B FPGAs (Modified new programming algorithm - 3.90 (built 0623))
Programming complete.
ATE Data: -55 °C, 25 °C, and +125 °C. One failure, S/N 80063: K Antifuse
Test Step KM4-1
Duration: 250 hours
Electrical Environment: VCCA=2.75V; Undershoot (average) = -1.0 volts. CLKIO = 8 MHz (57 SSO's); CLKArray = 32 MHz (100 % toggling); Delay Line = 1 MHz.
Thermal Environment: T = 150 ºC
Location of DUTs in Chamber
Status: Testing error, devices biased at +150 ºC. No antifuse damage detected, leakage currents increased.
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Last Revised:
May 12, 2006
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Richard Katz
