The NASA design and test is heavily based on the "Industry Tiger Team's" work and there is much in common. There are, however, a number of differences. The table below highlights a number of the significant differences.
| Industry Tiger Team | NASA | |
| ATE Testing: Temperature | Room temperature only | -55 ºC, 25 ºC, and +125 ºC prior to start of testing and at each key point. |
| ATE Testing: Coverage | Full internal coverage; subset of I/O parameters. | Full internal coverage and complete read and record coverage of I/O parameters. |
| In-Chamber Environment: Temperature | Mostly room temperature. | Steps at -55 ºC and +125 ºC |
| In-Chamber Environment: Voltage | Mostly nominal 2.5VDC. | Starts at the recommended maximum of 2.75 VDC. |
| Loading (A maximum fanout of 24 permitted by design rule checker) | Maximum fanout of 16. | 23 nets have fanout of 29 and 1 net with fanout of 28. |
| Device Stimulation | Three internal ring oscillators; frequency varies with device temperature, voltage, and individual device. | External clock generation and division making stimulation independent of temperature and voltage. |
| Clock Usage | One routed array clock; HCLK static. | Routed array clock and HCLK both dynamically exercised. HCLK provides for tighter control of SSO/SSU stress. |
| Delay Measurement | Indirect - no mechanism to break ring and measure delay directly. Significant startup stabilization time. | Direct propagation delay measurement; no startup stabilization issues. |
| I/O Standards | All TTL | A combination of TTL and CMOS I/O configurations |
| Place and Route | Mostly automatic, some manual placement of the ring oscillator circuits. | Shift register R-Cells manually placed to improve utilization of Long Vertical Tracks (LVT) and Long Horizontal Tracks (LHT). I/O driving R-Cells manually placed for tighter control of SSO/SSU stress. |
Home - NASA Office of Logic Design
Last Revised:
October 25, 2004
Digital Engineering Institute
Web Grunt:
Richard Katz
