NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Independent NASA Test of
Actel SX-A, SX-S, and SX-SU
Field Programmable Gate Arrays (FPGAs)

KU3: Parts Information

Device Programming – Completed

• Programming yield = 158/160 (98.75%)

• Yield loss was due to “Invalid Electronic Signature”

 

KU3/4 Test Vehicle Information

• Device: RTSX32SU – CQ208

• Wafer Lot / Date code: D1JW21 / 0519

• Per lot size: 150 + 2 (spares) + 1 (control unit)

• NASA2 Design

 

	KU1/KU2	KM1/KM2	KM3/KM4	KU3/KU4
Part #	RTSX32SU - CQ208	RT54SX32S - CQ208	RT54SX32S - CQ208	RTSX32SU - CQ208
Package	CQ208	CQ208	CQ208	CQ208
Foundry	UMC	MEC	MEC	UMC
Silicon Rev	Original			PolyResize
Algo	Original	New	Modified New	UMA
Software				SAL
Quantity	300	300	300	300
Pattern	NASA1	NASA1	NASA1	NASA2

 

Definitions:

 

Modified New Algorithm =  Targets low current antifuses; increase soak time

UMA (UMC Modified Algorithm) =  Targets low current antifuses; increase soak time

SAL (S-Antifuse Loading) =  Reduces peak currents by adding capacitance

NASA2 =  Pattern that focuses on single and double cases of S-Antifuses and B-Antifuses

<Operating Temperature

 =   LTOL:  T_A = -55 ºC   T_J = -20 ºC

=   HTOL:  T_A = 125 ºC   T_J = 146 ºC

<Stimulus for DUTs are generated by the NASA Driver card on each burn-in board

=   CLKA / CLKB =  8 MHz (HTOL)

=   CLKA / CLKB = 16 MHz (LTOL)

<Power Supplies

  =   NASA Driver card = 5.0V

   =   V_CCA = 2.5V to 3.0V  (view Test Plan Summary)

=   V_CCI  = 4.0V

 

 

Home Page for Independent NASA Test of Actel SX-A, SX-S, and SX-SU FPGAs

Home - NASA Office of Logic Design
Last Revised: May 12, 2006
Digital Engineering Institute
Web Grunt: Richard Katz