NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Independent NASA Test of
Actel SX-A, SX-S, and SX-SU
Field Programmable Gate Arrays (FPGAs)

This page is used for the official dissemination of test status, results, and reports.

Analysis of S/N 50718: Out of family I_CCA

Summary:

The mean I_CCA for KU1 is 461 µA with a standard deviation of 52 µA.  S/N 50718 read approximately 1.8 mA.  While this value is within the specification value of 25 mA (I_CCA + I_CCI) the device was removed from the population prior to the beginning of the stress tests.  Preliminary analysis indicates that this is not a programmed antifuse related matter but is an internal short.  ESD is suspected and the failure analysis will be completed.

History

• Passed programming
• Passed three temperature ATE testing
• Engineering analysis flagged the device as "out of family" with  an I_CCA of approximately 1.8 mA.
• TCK level sensitivity
  • TCK = '1' Þ 60 µA
  • TCK = '0' Þ 1.8mA
• 1st Suspect: sensitive ESD device, transistor N3b in TCK pad circuit
  • TCK schematic examination revealed TCK signal path does not utilize N3b
• 2nd Suspect: 2-input NOR gate (NMOS transistor N2– schematic next slide)
  • Transistor N2 is in the direct signal path of TCK
  • FIB (Focused Ion Beam) pads added at multiple TCK signal path nodes
  • Micro probing confirmed:
    • TCK output signal to the IEEE 1149.1 circuitry stuck near high voltage level
    • 2-Input NOR Gate in TCK input circuit not functioning
• De-processing to bare silicon revealed ESD in TWO NMOS transistors
  • Primary site– N2 Transistor of 2-Input NOR Gate (schematic next slide)
  • Secondary site– N3b transistor in user input signal path circuitry from TCK pin

Figure 1. TCK I/O Schematic with FIB pad locations

 

Figure 2, below, shows the following:

• High resolution SEM image from a 45° tilt at transistor N2 location
• N2 is within the 2-input NOR gate circuit in the signal flow path for TCK clock
• Photo is post HF strip to the silicon level
• Revealed signatures of damage that were obscured by overlaying layers

Figure 2. ESD Damage at Primary site

Figure 3A, below, shows the following:

• High resolution SEM image of transistor N3b
• N3b is an NMOS pull down within the first stage inverter of the user I/O input path
• For this NASA design this path is not functionally used
• Photo is pre-Oxide etch

Figure 3A. ESD Damage at secondary site (1 of 2)

Figure 3B, below, shows the following:

• High resolution SEM from a 45° tilt of Transistor N3b
• N3b is not functionally utilized for the signal flow path of TCK
• Photo is post HF strip to the silicon level
• More damage observed beyond pin hole observed with gate oxide in place

Figure 3B. ESD Damage at secondary site (2 of 2)

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Last Revised: February 28, 2005
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